Method for decreasing disc defect in chemicomechanical copper grinding

Abstract

This invention provides a reducing conductance structure dishing and erosion method in chemical mechanical grinding containing at least a dielectric layer with at least a dielectric window hole; forming a barrier layer on dielectric layer and the window hole; forming a conductive layer such as a copper layer on the barrier layer to fill in the dielectric window hole to form a conductive structure and removing part of conductive layer to expose part of the barrier layer to be polished as well as the conductive structure. With a reacted reagent so as to form a metal compound on the conductive structure prevented from dishing or erosion.

Description

(1) Technical field [0001] The present invention relates to a method for manufacturing semiconductor integrated components, in particular to a method for planarizing conductive copper wires and internal connections using a chemical mechanical process. (2) Background technology [0002] As the overall size of integrated circuits shrinks, the performance of internal components tends to be mixed, which is a natural characterization of semiconductor physics; that is, the speed and functional capabilities of components will increase simultaneously. In any case, the speed of the entire circuit is more dependent on the delay speed of the signal on the interconnection lines connecting the internal components. With the advent of extremely large and ultra-large integrated circuits, it is more and more important to form the internal connection conductors between components and the metal conductors between circuits in semiconductors to have high signal transmission and low resistance va...

AI Technical Summary

Problems solved by technology

The unevenness caused by dishing is due to the different polishing rates of different materials in the chemical mechanical polishing process, which is a challenge for the semiconductor industry

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