Semiconductor storage device and semiconductor integrated circuit device

Abstract

In a DRAM memory cell including an access Tr and a cell capacitor, a depletion type MOSFET is used for each of the access Tr and the cell capacitor. Thus, an operation margin can be increased and the number of necessary power supplied can be reduced, compared to a known DRAM.

Description

technical field [0001] The present invention relates to a semiconductor storage device; in particular, to a dynamic semiconductor storage device formed by logic process and a semiconductor integrated circuit device provided with the dynamic semiconductor device and a logic circuit. Background technique [0002] In recent years, the dynamic semiconductor memory device (DRAM) has been progressing toward the increase in capacity and miniaturization, and at the same time, the drive voltage has been reduced. The drive voltage is 1.8V at 0.18μm processing technology, and 1.8V at 0.15μm processing technology. It is 1.5V, especially when it is 1.2V in 0.13μm processing technology, and it has gradually approached 1V. [0003] In this case, various efforts have been made in the DRAM circuit to secure an operating margin at low voltage. For example, in a DRAM composed of one transistor and one capacitor (DRAM composed of 1T1C) or an NMOS memory cell type DRAM, the threshold voltage (h...

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Problems solved by technology

Therefore, when implementing these configurations, not only the circuit is complicated, but also there is a disadvantage that the chip area on the LSI is significantly increased due to the need for a bias circuit and a driver circuit.

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