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Method for making flash memory

A manufacturing method and flash memory technology, applied in the field of flash memory manufacturing, can solve the problems of shortening the channel length, affecting the electrical performance of the memory cell, etc., to achieve the effects of improving the coupling rate, reducing the cost, and simplifying the manufacturing process

Inactive Publication Date: 2004-07-28
POWERCHIP SEMICON CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, reducing the gate length will shorten the channel length (ChannelLength) under the tunnel oxide layer, which will easily cause abnormal electrical penetration (PunchThrough) between the drain and source, which will seriously affect the electrical properties of the memory cell. Performance
In addition, in the manufacturing process of flash memory, the photolithography process also has the problem of so-called critical dimensions, which limits the reduction of the memory cell size.

Method used

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  • Method for making flash memory
  • Method for making flash memory
  • Method for making flash memory

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Embodiment Construction

[0025] Please refer to Figure 1A , providing a substrate 100, such as a silicon substrate. Then, a tunnel dielectric layer 102 , a conductive layer 104 and a mask layer 106 are sequentially formed on the substrate 100 . The material of the tunnel dielectric layer 102 is, for example, silicon oxide, and its thickness is, for example, about 50 angstroms to 100 angstroms. The tunnel dielectric layer 102 is formed by thermal oxidation or low pressure chemical vapor deposition (LPCVD), for example.

[0026] The conductor layer 104 on the tunnel dielectric layer 102 is made of, for example, doped polysilicon, and its formation method is, for example, low-pressure chemical vapor deposition (LPCVD), using silane as a gas source to deposit a polysilicon layer. Afterwards, a dopant implantation process is performed to form. Wherein, the operating temperature of the deposition process is between 575 and 650° C., and the operating pressure is approximately between 0.3 and 0.6 Torr.

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Abstract

The invention provides a flash memory making method, firstly providing a semiconductor substrate with tunnel dielectric, conductor and masking layers in sequence, then patternizing these layers to form trenches in the substrate, then forming insulating layer in the trenches, wherein the surface of the insulating layer is between the conductor layer and the substrate, then forming the conductor gap wall, wherein the conductor layer and the gap wall compose the floating grid, and then removing the masking layer, forming the grid-grid dielectric layer on the floating grid and then forming the control grid on the substrate.

Description

technical field [0001] The invention relates to a method for manufacturing a flash memory, in particular to a method for manufacturing a flash memory with a self-aligned floating gate. Background technique [0002] Flash memory elements have the advantages of being able to store, read, and erase data multiple times, and the stored data will not disappear after power failure, so it has become a widely used in personal computers and electronic devices. memory components. [0003] A typical flash memory element is generally designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a polysilicon floating gate (Floating gate) for storing charges, silicon monoxide / nitride A dielectric layer of silicon oxide / silicon oxide (Oxide-Nitride-Oxide, ONO) structure, and a polysilicon control gate (Control Gate) for controlling data access. When programming or erasing the flash memory element, apply appropriate voltages to the source region, drain regio...

Claims

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Application Information

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IPC IPC(8): H01L21/8239H01L21/8246
Inventor 洪至伟宋达黄明山
Owner POWERCHIP SEMICON CORP