Great power MOSFET device and its manufacture

Abstract

The great power MOSFET device includes one drain formed in the silicon substrate; one epitaxial layer formed on the silicon substrate; one well layer formed on the epitaxial layer; one source contact area formed on the well layer; and two channel type gates formed through photoetching the source contact area and the well layer until the said epitaxial layer. Oxide is formed on the side walls of the channels and polysilicon is deposited inside the channels. The device includes also one embolism, which is formed with the channel type gates as mask and through etching partial source contact area until reaching the upper part of the well layer and configuring the second conducting re-doped ion in self-aligning mode. The embolism is below the etched partial source contact area and not in the same horizontal plane with the source contact area and reaches inside the well layer.

Description

technical field [0001] The present invention relates to a trench type power metal oxide semiconductor field effect transistor (Trenchpower MOSFET) with reduced on-resistance value, reduced current fast reverse (snap-back) and increased avalanche breakdown (avalanche breakdown) current capability ) device and method of manufacturing the same, and more particularly, to a dual-ditch gate power metal oxide semiconductor field effect transistor device having excellent quality and high reliability, which can reduce the value of on-resistance and improve resistance to avalanche shock wear current. Background technique [0002] In order to achieve low on-resistance (R DSON ), most of them adopt trench technology, especially to make the channel resistance value (R ch ), epitaxial layer resistance (R epi ) and junction resistance (R j ) is reduced to obtain a lower on-resistance value, and a double-ditch gate design is often used. However, the manufacture of trench power MOSFET d...

AI Technical Summary

Problems solved by technology

Although the device can use self-alignment technology to reduce manufacturing steps and use rounded corners to improve leakage, the current in the epitaxial layer is still concentrated directly under the double gate, making the current channel under the well layer narrow and inconvenient. Even, the on-resistance value cannot be further reduced, especially in the prevention of rapid reverse current and avalanche breakdown without any improvement

[0003] In a known power MOSFET device (taking N channel as an example, not shown in the figure), in order to make the on-resistance value (R DSON ) is reduced, and a high doping concentration P is often added to the source contact area + The plug (plug) is used to reduce the contact resistance value (Rc), but due to the P + plug with source N + The doped region is at the same level and when the reverse leakage current is generated, the reverse leakage current is changed from N - The epitaxial layer flows through the P - Well and P + plugged to the source, while the P - well with P + A voltage drop occurs between the plugs. When the voltage drop is greater than 0.6 volts, the PN parasitic diode will be turned on and a large amount of reverse leakage current will be generated, so that the phenomenon of rapid current reversal occurs, and the large amount of leakage current is generally concentrated in the P well and N - At the interface of the epitaxial layer, the current of avalanche breakdown is caused, which makes the interface generate high temperature and damages the power MOSFET device

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