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Polishing liquid with nanometer SiO2 abrasive for SiO2 medium in multilayer wiring of VLSI

A large-scale integrated circuit, multi-layer wiring technology, applied in polishing compositions containing abrasives, circuits, electrical components, etc., can solve the problems of difficult cleaning, high price, high viscosity, etc., to avoid scratches, avoid collapse edge, enhance the effect of chemical action

Inactive Publication Date: 2007-01-03
HEBEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Like other foreign products, there are disadvantages such as high viscosity and difficult cleaning
In addition, existing commercial SiO 2 Medium hydrosol polishing fluid is generally more expensive

Method used

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  • Polishing liquid with nanometer SiO2 abrasive for SiO2 medium in multilayer wiring of VLSI
  • Polishing liquid with nanometer SiO2 abrasive for SiO2 medium in multilayer wiring of VLSI

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] Prepare 1375g SiO2 2 Abrasive polishing fluid.

[0051] To 1000g 50wt% SiO with 15nm particle size and particle size dispersion of ±2.5nm 2 Add 40gJFC, 40gFA / O type I active agent, 50gFA / O chelating agent to the hydrosol solution and stir and mix evenly; and add 30g dihydroxyethylethylenediamine to the above mixed solution before production and processing, stir evenly, and then add 15g KOH Dilute it with 200g of deionized water, add it to the above mixture, and stir evenly; the pH value of the prepared polishing solution is 10.5-13.5.

Embodiment 2

[0053] Prepare 1495g SiO 2 Abrasive polishing fluid.

[0054] To 1000g 40wt% SiO with 20nm particle size and particle size dispersion of ±2.5nm 2 Add 40gJFC, 40gFA / O type I active agent, 50gFA / O chelating agent to the hydrosol solution and stir and mix evenly; and add 40g triethanolamine to the above mixed solution before production and processing and stir evenly, then dilute 25gKOH with 300g deionized water Then add it to the above mixture and stir evenly; the pH value of the prepared polishing solution is 10.5-13.5.

Embodiment 3

[0056] Prepare 1555g SiO 2 Abrasive polishing fluid.

[0057] To 1000g 45wt% SiO with 25nm particle size and particle size dispersion of ±2.5nm 2 Add 60g HJFC or O-20 (C 12-18 h 25-37 -C 6 h 4 -O-CH 2 CH 2 O) 70 -H), add 45gOπ-10 ((C 10 h 21 -C 6 h 4 -O-CH 2 CH 2 O) 10 -H), O-20(C 12-18 h 25-37 -C 6 h 4 -O-CH 2 CH 2 O) 70 -H), one or more surfactants of OS-15, add 50gFA / O chelating agent and stir and mix uniformly; , and then dilute 20g KOH with 300g deionized water and add it to the above mixture, stir evenly; the pH value of the prepared polishing solution is 10.5-13.5.

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PUM

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Abstract

The present invention is one kind of polishing liquid with nanometer SiO2 abrasive for SiO2 medium in multilayer wiring of VLSI. The polishing liquid consists of SiO2 hydrosol as abrasive 20-45 wt%, composite alkali 0.5-5.5 wt%, penetrant 1.0-10 wt%, surfactant 1.0-10 wt%, chelating agent 0.5-10 wt% and the deionized water for the rest. All the materials are mixed gradually through stirring to form the polishing liquid. The polishing liquid has high polishing efficiency, low cost and less pollution.

Description

technical field [0001] The invention relates to a chemical mechanical polishing liquid used in the field of microelectronic processing, in particular to a kind of ultra-large-scale integrated circuit multilayer wiring SiO 2 Dielectric nano-SiO 2 Abrasive polishing fluid. Background technique [0002] At present, the rapid development of the integrated circuit manufacturing industry has become one of the most important high-tech technologies to promote the development of national economy and social informatization. IC integration has reached hundreds of millions of devices / chip. The multi-layer wiring of the IC interconnection process has reached more than ten layers, and the components in the IC tend to be smaller in feature size, and the structure is miniaturized, thinned and multi-layer three-dimensional wiring is highly concentrated. In order to achieve multi-layer IC wiring and meet high-resolution lithography exposure accuracy, each layer of silicon dioxide (SiO2) in...

Claims

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Application Information

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IPC IPC(8): C09G1/02H01L21/306H01L21/768
Inventor 刘玉岭孙鸣
Owner HEBEI UNIV OF TECH
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