Method for making vertical double diffusion FET compatible conventional FET
A vertical double-diffusion, FET technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem that the control chip has a reduced ability to monitor overheating of the output chip, increased circuit reliability, and increased packaging costs. and other problems, to achieve the effect of solving reliability degradation, realizing high voltage and high current control, and low power consumption
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[0037] Under this platform, we realized the integration of control circuit and output high voltage VDMOS on the chip area of 2000*2200μm. The specific implementation is as follows:
[0038] 1.) High-concentration P+ implantation, pushing junction depth: The concentration and junction depth here have a great impact on the withstand voltage of the entire die. The specific concentration and junction depth should be adjusted appropriately according to the corresponding layout design.
[0039] 2.) Inject PWELL1 in the low-pressure area, and pre-push the junction depth: here is only a pre-push junction depth, and the junction depth should not be pushed too deep. Because there are still many high-temperature processes behind, the junction will be further deepened.
[0040] 3.) NWELL implantation in low-voltage area, pre-push junction depth: PWELL and NWELL for low-voltage CMOS are added before ACTIVE (active area). The junction depth of PWELL and NWELL here should not be pushed ...
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