Semiconductor back-end linked thread using glass contained F-Si as dielectric substance

Abstract

This invention discloses one semiconductor back end connection by use of fluorine-containing silicon glass as medium, which comprises the following steps: a, forming metal lines; b, growing oxidation with high reflection rate as underlay oxidation layer; c, depositing FSG as medium to cover one layer of normal reflection rate silicon oxidation or tetraethoxysilane; d, flattening the compound film by FSG, silicon oxidation or tetraethoxysilane; e, growing one layer of high reflection oxidation as cover layer in flatter silicon surface; f, opening hole as tungsten plug; g, removing redundant tungsten and diffuse block layer; h, depositing one layer of metal.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor back-end wiring using fluorine-containing silicon glass as a dielectric. Background technique [0002] With the further development of semiconductor technology, nanotechnology is becoming more and more important, which also puts forward new requirements for the integration of subsequent processes. In the case of nanometer technology, it is necessary to further reduce the circuit delay caused by the parasitic capacitance of the subsequent metal interconnection and dielectric. Therefore, in the prior art, a new low-resistance material copper and a low-permittivity dielectric material such as FSG, that is, fluorine-containing silicon glass, are used in the semiconductor back-end wiring process. [0003] The schematic diagrams of the semiconductor back-end wiring process using fluorine-containing silicon glass as the dielectric in the prior art are shown in...

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Problems solved by technology

[0004] However, the prior art process method has the following problems: firstly, as shown by the mark A in Fig. 3b, due to its poor conformality, the thickness of the liner oxide layer grown in situ is less than the nominal value at the corner of the line, which will cause The metal line integrity is severely damaged during the subsequent FSG deposition, as shown by the marker B in Figure 3c

[0005] Secondly, in order to maintain the integrity of the metal lines, the pad oxide layer grown in-situ must exceed a certain thickness, but this will cause a decrease in filling performance and leave small voids between the metal lines, which will cause problems in the subsequent manufacturing process. Causes potential metal growth in between, causing leakage between metal lines, which greatly reduces the yield; in addition, due to its high dielectric constant relative to FSG, the parasitic capacitance between metal lines increases, reducing the speed of the final circuit

[0006] Third,

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