Method for analyzing BEOL testing chip on-line failure
A failure analysis and chip technology, applied in electronic circuit testing, single semiconductor device testing, semiconductor/solid-state device testing/measurement, etc., can solve the problems of time-consuming and labor-intensive success rate, inability to optimize, low success rate, etc., to improve analysis efficiency and success rate, improve efficiency and accuracy, avoid the effect of destructive analysis
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[0011] Fig. 1 is a schematic flow chart of the present invention. As shown in Figure 1, firstly, a silicon wafer defect detection machine for any layer of metal line engineering is used for defect detection on the silicon wafer, and the detected defects are classified, and 5-10 points are selected at different positions of the silicon wafer It is easy to find defects with a size less than 5 microns under the scanning electron microscope, and generate the KRF format result file ins.krf; then use the characteristic tester to test the open circuit and short circuit of the silicon wafer, and also generate the KRF format failure position file pcm. krf, in the above process, it is necessary to ensure that the silicon wafer origin and the chip origin of ins.krf and pcm.krf are consistent; Figure 2 is a schematic diagram of multiple virtual defects generated by splitting the failure structure of the characteristic test. As shown in Figure 2, each failed test structure in pcm.krf is de...
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