Method for manufacturing ic-embedded substrate

Abstract

The invention provides a method for manufacturing an IC-embedded substrate without generating damages on a semiconductor IC chip embedded in a resin layer due to heating and weighting (stress), and is able to manage increase and finely spaced of number of pad electrodes. Firstly, a copper foil (12) disposed on either side of the core substrate (11) is selectively removed by photolithography and etching, whereby a conductor pattern (13) comprising wiring and lands is formed on the core substrate (11). Next, after a semiconductor IC chip (14) is mounted face up in a prescribed region on the core substrate (11), it is embedded in a resin sheet (16). Then, a copper foil (17) formed on a surface of the resin sheet (16) is selectively removed by shape-maintained machining, as as to form a mask pattern for forming an aperture. Thereafter, the aperture is formed by a sand-jetting processing in which the copper foil (17) applied with shape-maintained machining is used as the mask.

Description

technical field [0001] The present invention relates to a method for manufacturing an IC-embedded substrate, in particular to a method for forming a through-hole of a multilayer substrate with an IC embedded therein. Background technique [0002] Conventionally, as a high-density mounting structure of a printed wiring board, a structure in which a printed wiring board has a multilayer structure and a semiconductor IC chip is embedded therein is known (see Japanese Patent Application Laid-Open No. 2001-237347). In addition, as a method of exposing a pad electrode of a semiconductor IC chip built in a printed wiring board, for example, there is a method of forming a through hole directly above the pad electrode by laser processing (refer to Japanese Patent Application Laid-Open No. 9-321408 Publication) and the method of polishing the entire surface of the embedding resin layer of the semiconductor IC chip to expose the pad electrodes (refer to Japanese Patent Laid-Open No. 20...

AI Technical Summary

Problems solved by technology

First, since a load is applied to the substrate when polishing the entire surface of the embedded resin, there is a problem that the semiconductor IC chip may be damaged and the yield may deteriorate.

In addition, the condition setting range of the grinding amount is narrow, and it is very difficult to control the grinding variation to a minimum

Furthermore, when embedding a semiconductor IC chip with different heights of the pad electrodes, all the pad electrodes cannot be exposed.

In addition, when using semi-addition to carry out the electrical connection of the pad electrode and the wiring pattern, it is necessary to carry out no-field electroplating and electrolytic plating in sequence on the ground resin surface, but due to the gap between the ground resin surface and the no-electric field The bonding strength between them is low, so the deterioration of reliability occurs

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