Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process

Abstract

A method of forming an annealed high-K metal oxide transistor gate structure is disclosed. A metal oxide layer is formed over a semiconductor substrate. The metal oxide layer undergoes a buffered annealed process in an oxygen atmosphere to anneal the metal oxide layer at or below the thermodynamic chemical equilibrium of SiO / SiO2 and at or above the thermodynamic chemical equilibrium of the metal oxide layer.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to the field of semiconductor devices, and more specifically to a fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant. [0003] 2. Description of the Related Art [0004] As the dimensions of the MOS transistor are scaled down, the thickness of its gate oxide, typically SiO2, decreases accordingly. Reducing the SiO2 layer to an ultrathin thickness results in charge carrier leakage by tunneling conduction as the ultrathin SiO2 gate oxide layer no longer functions as an effective insulator. [0005] Tunneling conduction also causes a faster dissipation of stored charge resulting in, for example, shortened battery life in portable devices such as cellular telephones and laptop computers. Typically, the gate dielectric layer used in a MOS transistor is an SiO2 layer which has a dielectric constant of 3.9. Alternative gate oxide m...

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Benefits of technology

[0014] The present invention addresses the noted problems above and provides a method of fabricating a semiconductor device such as a MOSFET (metal-oxide semiconductor field effect transistor) utilizing a metal oxide dielectric material possessing a dielectric constant greater than SiO2. Specifically, the invention provides a processing sequence for the post-deposition annealing of a high-K metal oxide dielectric layer to produce a metal oxide dielectric layer having a lower fixed charge (i.e., a high-K metal oxide layer that is closer to its stoichiometric point), resulting in a transistor device with higher carrier mobility and drive current.

[0015] To this end, the present invention provides a method and resulting structure having a metal oxide dielectric layer, fabricated over a substrate, which is annealed in a buffered oxygen atmosphere. An interfacial layer such as SiO2 is optionally present between the metal oxide dielectric layer and substrate. The metal oxide dielectric layer is annealed by controlling the partial pressure of oxygen as a function of anneal temperature such that annealing occurs under conditions at or below the thermodynamic chemical equilibrium for SiO / SiO2 and at or above the thermodynamic chemical equilibrium for the metal oxide dielectric layer. As a result of the buffered annealing, a high-K metal oxide dielectric layer with a reduced fixed charge and substantially improved carrier mobility characteristics is attained.

Problems solved by technology

Reducing the SiO2 layer to an ultrathin thickness results in charge carrier leakage by tunneling conduction as the ultrathin SiO2 gate oxide layer no longer functions as an effective insulator.

Tunneling conduction also causes a faster dissipation of stored charge resulting in, for example, shortened battery life in portable devices such as cellular telephones and laptop computers.

However, current high-K dielectric gate layers result in devices that suffer from low carrier mobility and drive current.

Such processing steps can result in an undesirably thick SiO2 interfacial layer due to reoxidation of the Si / SiO2 (silicon / silicon dioxide) interface.

Therefore, the presence of a significantly reoxidized thicker SiO2 layer is undesirable.

Moreover, a high-K gate dielectric is typically formed under conditions that result in anomalies in the overall charge of the fabricated high-K gate dielectric.

Growing high-K gate dielectrics naturally results in deviations from its ideal stoichiometric state since its formation occurs under conditions far from its thermodynamic equilibrium.

Realistically however, a net charge of zero is not obtained utilizing present fabrication methods and techniques.

Additional problems arise when utilizing a metal oxide in lieu of SiO2 as the gate dielectric material.

Annealing at conditions above line 10 results in significant reoxidation of the underlying SiO2 layer which is undesirable as noted above.

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