Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process

a technology of metal oxide dielectric material and fabrication process, which is applied in the direction of coating, capacitor, chemical vapor deposition coating, etc., can solve the problems of shortened battery life of portable devices such as cellular telephones and laptop computers, leakage of charge carriers, and longer functions as effective insulators, so as to achieve the effect of driving current and high carrier mobility

Inactive Publication Date: 2005-02-24
GREEN MARTIN L +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0014] The present invention addresses the noted problems above and provides a method of fabricating a semiconductor device such as a MOSFET (metal-oxide semiconductor field effect transistor) utilizing a metal oxide dielectric material possessing a dielectric constant greater than SiO2. Specifically, the invention provides

Problems solved by technology

Reducing the SiO2 layer to an ultrathin thickness results in charge carrier leakage by tunneling conduction as the ultrathin SiO2 gate oxide layer no longer functions as an effective insulator.
Tunneling conduction also causes a faster dissipation of stored charge resulting in, for example, shortened battery life in portable devices such as cellular telephones and laptop computers.
However, current high-K dielectric gate layers result in devices that suffer from low carrier mobility and drive current.
Such processing steps can result in an undesirably thick SiO2 interfacial layer due to reoxidation of the Si/SiO2 (silicon/silicon dioxide) interface.
Therefore, the presence of a significantly reoxidized thicker SiO

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  • Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process
  • Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process
  • Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process

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Embodiment Construction

[0023] The present invention will be understood from the following detailed discussion of exemplary embodiments which is presented in connection with the accompanying drawings.

[0024] The present invention provides a method of fabricating a semiconductor device having a metal oxide dielectric layer with a high dielectric constant (high-K), annealed with a buffered anneal process. An interfacial layer such as SiO2 is optionally present between the metal oxide layer and substrate during the buffered anneal process. The buffered anneal process anneals the metal oxide dielectric layer in an oxygen atmosphere in which the partial pressure of oxygen is controlled as a function of anneal temperature such that annealing occurs under conditions at or below the thermodynamic chemical equilibrium for SiO / SiO2 and at or above the thermodynamic chemical equilibrium for the metal oxide dielectric layer.

[0025] In the following description, specific details such as layer thicknesses, material comp...

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Abstract

A method of forming an annealed high-K metal oxide transistor gate structure is disclosed. A metal oxide layer is formed over a semiconductor substrate. The metal oxide layer undergoes a buffered annealed process in an oxygen atmosphere to anneal the metal oxide layer at or below the thermodynamic chemical equilibrium of SiO/SiO2 and at or above the thermodynamic chemical equilibrium of the metal oxide layer.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to the field of semiconductor devices, and more specifically to a fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant. [0003] 2. Description of the Related Art [0004] As the dimensions of the MOS transistor are scaled down, the thickness of its gate oxide, typically SiO2, decreases accordingly. Reducing the SiO2 layer to an ultrathin thickness results in charge carrier leakage by tunneling conduction as the ultrathin SiO2 gate oxide layer no longer functions as an effective insulator. [0005] Tunneling conduction also causes a faster dissipation of stored charge resulting in, for example, shortened battery life in portable devices such as cellular telephones and laptop computers. Typically, the gate dielectric layer used in a MOS transistor is an SiO2 layer which has a dielectric constant of 3.9. Alternative gate oxide m...

Claims

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Application Information

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IPC IPC(8): H01L21/02H01L21/28H01L21/314H01L21/316H01L29/51
CPCH01L21/02178H01L21/02263H01L21/02304H01L21/02337H01L21/28185H01L29/518H01L21/31612H01L21/31616H01L28/56H01L29/513H01L29/517H01L21/28194
Inventor GREEN, MARTIN L.WILK, GLEN D.
Owner GREEN MARTIN L
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