Semiconductor memory device with ability to adjust impedance of data output driver

Abstract

A semiconductor memory device for performing an OCD calibration control operation in order to adjust a data output impedance, including: means for decoding an address signal to generate an OCD default control signal, an OCD operation signal and plural data; means for receiving a plural-bit data to generate an OCD control code; means for receiving the OCD control code and the OCD operation signal to generate a plurality of impedance adjustment control signals; and means for receiving the plural data and adjusting the data output impedance in response to the plurality of impedance adjustment control signals.

Description

FIELD OF INVENTION [0001] The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of adjusting an impedance of a data output driver. DESCRIPTION OF PRIOR ART [0002] A dynamic random access memory (DRAM) has been improved continuously to increase its operational speed. Synchronizing an internal clock signal with an external clock signal is one of methods to improve an operational speed of the DRAM. Particularly, a DRAM which is operated in synchronization with the external clock signal is called a synchronous dynamic random access memory (SDRAM). [0003] The SDRAM performs a data access operation at a rising edge of the external clock signal. That is, the SDRAM can perform the data access operation once within one cycle of the external clock signal. [0004] Such an SDRAM that performs the data access operation once within one cycle of the external clock signal is particularly called a single data rate (SDR) SDRAM....

AI Technical Summary

Benefits of technology

[0048] It is, therefore, an object of the present invention to provide a semiconductor memory device having a circuit for adjusting impedance of a data output driver.

Problems solved by technology

However, the above-mentioned OCD calibration control operation is a newly introduced concept by the JEDEC and a circuit for performing the OCD calibration control operations has not developed yet.

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