Method of barrier layer surface treatment to enable direct copper plating on barrier metal

Abstract

Embodiments of a method of barrier layer surface treatment to enable direct copper plating without copper seed layer. In one embodiment, a method of plating copper on a substrate with a group VIII metal layer on top comprises pre-treating the substrate surface by removing a group VIII metal surface oxide layer and / or surface contaminants and plating copper on the pre-treated group VIII metal surface. Pre-treating the substrate can be accomplished by annealing the substrate in an environment with a hydrogen-containing gas environment and / or a non-reactive gas(es) to Ru, by a cathodic treatment in an acid-containing bath, or by immersing the substrate in an acid-containing bath

Description

CROSS-REFERENCE TO OTHER APPLICATIONS [0001] This application claims the benefit of U.S. provisional patent application serial No. 60 / 579,129, filed Jun. 10, 2004, which is incorporated herein by reference.BACKGROUND OF THE DISCLOSURE [0002] 1. Field of the Invention [0003] Embodiments of the invention generally relate to a method for barrier layer surface treatment to enable direct copper plating on barrier metal. [0004] 2. Description of the Background Art [0005] Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. The multilevel interconnects that lie at the heart of this technology require the filling of contacts, vias, lines, and other features formed in high aspect ratio apertures. Reliable formation of these features is very important to the success of both VLSI and ULSI as well as to the continued effort to increase circuit de...

AI Technical Summary

Benefits of technology

[0013] Embodiments of the invention generally provide a method of barrier layer surface treatment to enable direct copper plating without copper seed layer. In one embodiment, a method of directly plating copper on a substrate with a group VIII metal layer on the substrate surface comprises pre-treating the substrate surface to remove a group VIII metal surface oxide layer and/or organic surface contaminants on the substrate surface to reduce a critical current density during plating, and plating a continuous and void-free copper layer on the pre-treated substrate surface in an acidic plating bath with a plating current density equaling to or greater than the critical current density.

[0014] In another embodiment, a method of directly plating copper on a substrate with a group VIII metal layer on the substrate surface comprises pre-treating the substrate surface by annealing the substrate in an environment with a hydrogen-containing gas and/or a gas(es) non-reactive to group VIII metal to reduce a critical current density during plating, and plating a continuous and void-free copper layer on the pre-treated substrate surface in an acidic plating bath with a plating current density equaling to or greater than the critical current density.

[0015] In another embodiment, a method of directly plating copper on a substrate with a group VIII metal layer on the substrate surface comprises pre-treating the substrate surface by annealing the substrate in an environment with a hydrog...

Problems solved by technology

Many conventional deposition processes do not consistently fill structures in which the aspect ratio exceeds 6:1, and particularly when the aspect ratio exceeds 10:1.

Additionally, as the feature widths decrease, the device current typically remains constant or increases, which results in an increased current density for such features.

Aluminum can also suffer from electromigration, leading to the formation of voids in the conductor.

However, as the interconnect sizes decrease and aspect ratios increase, void-free interconnect feature fill by conventional metallization techniques becomes increasingly difficult using CVD and / or PVD.

However, as the feature sizes become smaller, it becomes difficult to have adequate seed step coverage with PVD techniques, as discontinuous islands of copper agglomerates are often obtained in the feature side walls close to the feature bottom.

When the deposition thickness on the field is reduced to prevent throat closure, ALD and CVD techniques are also prone to generate discontinuities in the seed layer.

These discontinuities in the seed layer have been shown to cause plating defects in the layers plated over the seed layer.

In addition, copper tends to oxidize readily in the atmosphere and copper oxide readily dissolves in the plating solution.

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