Compositions and methods for high-efficiency cleaning of semiconductor wafers

Abstract

A composition including supercritical fluid and at least one additive selected from fluoro species, and primary and / or secondary amines, optionally with co-solvent, low k material attack-inhibitor(s) and / or surfactant(s). The composition has particular utility for cleaning of semiconductor wafers to remove post-ashing residues therefrom.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This is a continuation of the U.S. patent application Ser. No. 10 / 602,172 for “Compositions and Methods for High-Efficiency Cleaning of Semiconductor Wafers” filed on Jun. 24, 2003 in the name of Michael B. Korzenski et al., which is incorporated herein in its entirety. FIELD OF THE INVENTION [0002] The present invention relates to compositions and methods for high-efficiency cleaning of semiconductor wafers. DESCRIPTION OF THE RELATED ART [0003] The fabrication of multi-layer semiconductor circuits requires the deposition of multiple patterned layers of semiconductor, conductor and dielectric materials. Patterning is conventionally carried out by optical imaging of a photoresist layer formed from a composition containing a soluble polymer and a photoactive compound. Following patterning, deposition, and etching, the photoresist layer must be completely removed before the next processing step. [0004] Plasma ashing can remove photoresist...

AI Technical Summary

Benefits of technology

The supercritical fluid-based compositions demonstrate superior ability to remove residues from semiconductor wafers, including photoresist and post-ash materials, while minimizing attack on low-k dielectric layers, thereby improving cleaning efficiency and reducing environmental impact.

Problems solved by technology

Such removers, however, generate a large amount of hazardous waste that is harmful to the environment, and costly to dispose of, or treat.

As a further and specific problem attendant the use of conventional liquid-based cleaning and post-etch residue removal compositions, the geometric scale of features in semiconductor device architectures continues to diminish.

Thus, although liquid-based cleaning and post-etch residue removal integrated circuit processes are well-developed and accepted for device manufacturing, their future utility is highly questionable.

Apart from problems attendant the high surface tension of aqueous cleaning compositions, copper, porous, low-k multi-layers may require special, non-aqueous cleaning to eliminate aqueous contamination of the pores and consequent reduction of device yields when pore contaminants cannot be removed.

Additionally, the dielectric constant of low k materials is critical and aqueous contamination can negatively increase the dielectric constant.

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