Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses and related devices

Abstract

Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.

Description

CLAIM OF PRIORITY [0001] This application is related to and claims priority from Korean Patent Application No. 10-2005-0000192, filed on Jan. 3, 2005, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference as if set forth in its entirety. FIELD OF THE INVENTION [0002] The present invention relates to methods of fabricating semiconductor devices and related devices, and more particularly, to methods of fabricating semiconductor devices including NMOS and PMOS transistors and related devices. BACKGROUND OF THE INVENTION [0003] Semiconductor devices typically use discrete devices, such as metal oxide semiconductor (MOS) transistors as switching devices. Accordingly, in order to improve characteristics of semiconductor devices, high performance MOS transistors may be needed. As semiconductor devices become more highly integrated and operate at higher speeds, various approaches have been implemented to improve characteristics of the...

AI Technical Summary

Benefits of technology

[0007] Some embodiments of the present invention provide methods of fabricating semiconductor devices. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer.

Problems solved by technology

However, reduction in the channel length may result in a short channel effect, and a more complicated, expensive photolithography process may be used.

Furthermore, reduction in the thickness of the gate insulating layer may result in an increase in leakage current through the gate insulating layer, causing a deterioration in device performance.

Although the electron mobility in the tensile-strained silicon layer may be improved, the hole mobility may be detrimentally affected.

In other words, although performance of an NMOS transistor may be improved, performance of a PMOS transistor may deteriorate.

However, a problem may occur during the subsequent contact structure formation process.

Since the silicon nitride layers formed on the upper portions of the NMOS transistor and PMOS transistor have different thicknesses, defective openings may occur in the NMOS transistor, and over-etching may occur in the PMOS transistor.

Problems caused by over-etching may be more problematic where misalignment occurs during the contact hole formation.

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