Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom

Abstract

A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

Description

FIELD OF THE INVENTION [0001] The present invention relates generally to wafer bonding and more particularly to a method and system of bonding in a wafer packaging environment. RELATED APPLICATIONS [0002] U.S. patent application Ser. No. 10 / 690,224, entitled “X-Y Axis Dual-Mass Tuning Fork Gyroscope with Vertically Integrated Electronics and Wafer-Scale Hermetic Packaging,” filed Oct. 20, 2003. [0003] U.S. patent application Ser. No. 10 / 691,472, entitled “Method of Making an X-Y Axis Dual-Mass Tuning Fork Gyroscope with Vertically Integrated Electronics and Wafer-Scale Hermetic Packaging,” filed Oct. 20, 2003. [0004] U.S. patent application Ser. No. 10 / 770,838, entitled “Vertically Integrated MEMS Structure,” filed Feb. 2, 2004. [0005] U.S. patent application Ser. No. 10 / 771,135, entitled “Vertical Integration of a MEMS Structure with Electronics in a Hermetically Sealed Cavity,” filed Feb. 2, 2004. BACKGROUND OF THE INVENTION [0006] MEMS technology has been under steady development...

AI Technical Summary

Benefits of technology

[0017] A method of bonding two substrates to create a robust electrical and mechanical contact by using aluminum and germanium eutectic alloys is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as a standard foundry CMOS process; (5) this process is compatible with completely fabricated CMOS wafers as post process; (6) this process can provide for high density electrical interconnect; and (7) this process is highly controllable and provides for the smallest gap between two substrates. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

Problems solved by technology

Although hybrid integration can provide vertical MEMS devices, the cost tends to be high, since manual processing steps are usually required, and because hybrid integration is typically performed on single devices.

However, most of these processes have been limited to providing protection of a sensitive feature from post process handling, such as sawing, die bonding, testing, package, etc.

These materials have disadvantages in that because they are organic, they tend to outgas and so are unsuitable for forming hermetic enclosures, and also they are susceptible to solvents, or moistures which can lead to problems with long term reliability and drift of a device's performance.

Additionally, they are insulating materials and so are incapable of forming a conductive path between two substrates.

Several major drawbacks are that frit glass does not provide for electrical interconnection between the MEMS and cover, to achieve a hermetic seal interface, minimum of 400 micron seal ring width is required which makes small MEMS devices, such as resonators and optical devices, much larger than otherwise.

Although these processes are capable of doing / creating? hermetic seals and electrical interface, achieving fine features, small gaps and water uniformity are / is very challenging and will result in yield losses.

Hence it is not possible to specify one or two micron gap controls between the MEMS and CMOS substrates using this bonding methodology.

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