Metal gate mosfet by full semiconductor metal alloy conversion

Abstract

A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.

Description

TECHNICAL FIELD [0001] The present invention relates in general to the manufacture of integrated circuits and, more particularly, to a structure and method of making MOSFET devices having metal gates. BACKGROUND OF THE INVENTION [0002] Metal gate technology allows for improved MOSFET device performance over conventional semiconductor MOSFET devices using semiconductor gate electrodes, due to elimination of the depletion layer in the gate; thus, decreasing the electrical inversion oxide thickness, tinv, by about 3-5 Å without incurring a subsequent significant increase in gate oxide leakage current. Typically, semiconductor gate electrodes are formed from polysilicon (poly or poly-Si, amorphous Si, SiGe etc.). MOSFET devices with fully silicided gate electrodes (FUSI gates) allow for thinner electrical inversion oxide thickness, tinv resulting in improved device performance due to increased carrier density in the channel, and also improved control over short-channel effects. Recently...

AI Technical Summary

Benefits of technology

The present invention provides a method for making a semiconductor structure that leverages improved performance of metal gates achieved via full silicidation (FUSE) of a semiconductor gate without disrupting the electrical properties of the transistor. The method allows for the cost-effective integration of different types of transistors, such as fully silicided nFET and PFET devices, with partially silicided gate electrodes. The method also allows for the formation of a semiconductor structure with fully silicided and partially silicided gate conductors in the same semiconductor device. The invention also provides a semiconductor structure that includes a first one of an nFET and PFET device with a partially-silicided gate conductor and a second one of an nFET and PFET device with a fully-silicided gate conductor. The structure is formed by a method that includes removing portions of a planarized dielectric layer to expose semiconductor layers of gate stacks in the nFET and PFET regions, forming a metal-containing layer in contact with the semiconductor layers, and forming a fully silicided gate conductor in the nFET region and a partially silicided gate conductor in the PFET region.

Problems solved by technology

On the other hand, a p-type dopant has yet to be found that can significantly shift the workfunction towards the valence band edge; thus the technique of pre-doping fully silicided gates is less effective for PFET devices.

The use of different processes for silicidation of the nFET and PFET gate conductors makes integration of both nFET and PFET devices difficult, especially in tightly packed memory cells.

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