Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures

Abstract

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is related to commonly-assigned Application Ser. No. ______ , filed on even date herewith, entitled “SEMICONDUCTOR STRUCTURES WITH BODY CONTACTS AND FABRICATION METHODS THEREOF” and bearing Attorney Docket No. ROC920050178US1, which is hereby incorporated by reference herein in its entirety.FIELD OF THE INVENTION [0002] The invention relates generally to semiconductor structures and, in particular, to semiconductor structures with multiple vertical memory cells arranged to form a memory array and methods of forming such semiconductor structures. BACKGROUND OF THE INVENTION [0003] Dynamic random access memory (DRAM) devices are the most commonly used type of semiconductor memory and, thus, are found in many integrated circuit designs. DRAM devices are also frequently embedded into application specific integrated circuits, such as processors and logic devices. A generic DRAM device includes a plurality of substantially id...

AI Technical Summary

Benefits of technology

[0012] The present invention is generally directed to a semiconductor-on-insulator (SOI) structure that incorporates a body contact extending through the buried dielectric layer and, thereby, coupling an SOI body with an underlying semiconductor substrate and methods of forming such body contacts, desirably, with an ion implantation process. The structure improves the cell data retention time for a vertical memory cell in an SOI dynamic random access memory (DRAM) device by reducing floating body effects that, if uncompensated, may affect the memory cell access device and result in charge loss from the associated storage capacitor in the vertical memory cell. Specifically, charge carriers that would otherwise accumulate in the channel region of the access device are drained or discharged through a high-resistance leakage path defined by the body contact that extends to the underlying semiconductor substrate.

Problems solved by technology

Consequently, vertical memory cells lack the scaling problems with, for example, reducing the gate-oxide thickness and increasing the channel doping concentration encountered when scaling planar access devices to smaller sizes.

Floating body effects are known to significantly degrade cell data retention time, which is most evident in long data retention time memory cells.

Floating body effects also cause fluctuations in the threshold voltage for the memory cell arising from the charge build up, which is extremely detrimental to conventional operation of transistor-type access devices.

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