Content addressable memory

Abstract

An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a content addressable memory, and particularly to a construction for reducing current consumption and a peak current in a search operation and for speeding up the search operation.[0003]2. Description of the Background Art[0004]A CAM (Content Addressable Memory) has, in addition to a function of reading / writing data, a function of determining matching of stored data with supplied search data. One entry storing a search data word is configured by a plurality of CAM cells, and stores word bits of a search candidate. Each entry is provided with a match line coupled to corresponding CAM cells in parallel. When a search data word matches a stored data word, a corresponding match line is kept at a state of “1”. When mismatch occurs, the corresponding match line is driven to a state of “0”.[0005]By determining the voltage level of the match line, it is possible to determine whether the data cor...

AI Technical Summary

Benefits of technology

[0027]An object of the invention is to provide a content addressable memory that can reduce current consumption and can achieve a fast search operation even when a bit number of search data is large.

Problems solved by technology

Therefore, the search line has a large capacitive load.

Therefore, the charge and discharge currents of the search line and the match line are large, resulting in a problem that current dissipation and power consumption are large.

In the CAM and TCAM, as described above, the search line and the match line are charged and discharged in each search cycle, and the current consumption is large.

Therefore, a simultaneous operation current (peak current) is large, which may cause switching noises.

Therefore, signal amplitudes of the local and global match lines indicating a result of the match-detection are large, and such a problem arises that there is a limit in reduction of the current consumption and the reduction of the time required until settlement of the match result.

In this case, however, the operation speed of the transistor element determines the lower limit of the power supply voltage level, to pose the restriction on the increase in operation speed.

However, such a problem occurs that the match line in the match state is charged to the power supply voltage level, and the voltage amplitude thereof becomes large.

Therefore, the capacitance values must be adjusted between the match line and the capacitance element with high precision, and it is difficult to charge up precisely the match line in the match state to a desired intermediate voltage level.

However, no consideration is given to reduction of the capacitance of the search line.

Accordingly, the search line is charged from the intermediate voltage level to the power supply voltage level according to the search data, and such problem arises that as the number of entries increases, the load capacitance accordingly increases and the current consumption cannot be reduced.

Therefore, the voltage amplitude of the match line is large, resulting in a problem that the fast search operation and the reduced current consumption cannot be achieved.

In the construction disclosed in the publication 4, the CAM entry is divided and such a problem arises that the divided entries are precharged to different voltage levels, and it is difficult to achieve a uniform operation speed between the divided entries.

Further, the match line of each divided entry has the voltage amplitude of the power supply voltage level, so that the fast search operation cannot be achieved.

When the number of bits of the search data increases and accordingly the number of bits of the CAM cells of the entry increases, the load of the match line increases to increase the current consumption for precharging from the intermediate voltage level to the power supply voltage level.

However, no consideration is given to the restriction of the precharge current value.

Therefore, the bit line must be precharged to the power supply voltage level, resulting in a problem that the current consumption cannot be reduced.

Accordingly, the discharge speed of the sense node slows in the state of one-bit miss for the search data, resulting in a problem that the search operation cannot be performed fast.

This scheme results in a problem that adjustment of the load capacitances of the capacitance element and the match line cannot be made easily, similarly to the publication 2.

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