Variable address length compiler and processor improved in address management

Abstract

The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

Description

RELATED APPLICATION[0001]This application is a divisional of application Ser. No. 09 / 662,484, filed Sep. 14, 2000, which is a reissue application of application Ser. No. 08 / 587,338, now U.S. Pat. No. 5,809,306, which claims priority to Japanese Patent Applications 5-126212, filed on May 27, 1993, 5-129529, filed on May 31, 1993, and 5-247154, filed on Oct. 1, 1993, which are all incorporated herein by reference.BACKGROUND OF THE INVENTION[0002](1) Field of the Invention[0003]The present invention relates to a program converting unit for converting a high level language program into a machine language program and a processor for running the converted program, and more particularly, to such a processor improved in address management with various types of register groups including address and data registers.[0004](2) Description of the Related Art[0005]With the recent advancement in the field of electronic technology, data processors such as a microprocessor and a microcomputer have be...

AI Technical Summary

Benefits of technology

[0073]Accordingly, a first object of the present invention is to provide a program converting unit which adequately selects an operation code to generate an object program in accordance with a data bit-width and an application program's address space, which does not depend on a data bit-width, so as not to degrade operation efficiency caused by address calculation, and to provide a processor that runs the resulting object program.

[0074]A second object of the present invention is to provide a program converting unit that reduces the code size of a machine language program independently of a type of data variable when the application program does not have an arithmetic overflow or the application program is constructed to avoid the arithmetic overflow or the one that generates a compensation instruction corresponding to each type of data variable otherwise, and to provide a processor that runs the resulting compensation instruction.

[0075]A third object of the present invention is to provide a processor that reduces the program size by simplifying the operation code to execute a data-transfer instruction at a higher speed.

Problems solved by technology

Consequently, the performance efficiency is significantly degraded compared with a 16-bit non-segment-address processor.

However, on the other hand, programming efficiency is degraded because it is a programmer that selects one of the two pointer variables by checking the segment boundary.

Thus, if the 32-bit processor and compiler are employed, the hardware is not fully utilized, wasting the cost and running electricity.

In addition, the 32-bit processor always designates a 32-bit address in a program, and thus increases a program code size undesirably.

Also, the performance is degraded when a 16-bit data bus is used to connect the 32-bit processor to a memory compared with a 32-bit data bus.

However, the second conventional processor demands the size field in each data-transfer instruction, which further demands a size-field decoding function and enlarges an instruction code, or increases the code size.

Some compilers, however, may not judge the effective 16-bit width when the program uses 16-bit data.

However, this method demands the 32-bit notation even when 16-bit data are designated, and thus extending the instruction size and object code unnecessarily.

Thus, a processor that can access to correct data in the address space efficiently using the immediate data shorter than the address register has not been realized yet.

However, the number of the instructions increases considerably in the above way, which demands larger and more sophisticated hardware for the instruction decoding and execution.

However, the RISC compiler compiles the program using the character or short-integer data variables with a considerable number of the compensation instructions, which increases the code size of the resulting machine language program, and hence prolonging the data processing time.

In addition, there is no advantage using the compensation instructions when a program does not have the overflow, or a programmer avoids the overflow by checking the available range for each data variable.

Further, an integer data variable, besides the character and short-integer data variables, causes the same problem in a system where the bit-width of the register exceeds that of the integer data variable.

Since the integer data variables are most frequently used, the problem becomes far more serious.

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