TSV for 3D packaging of semiconductor device and fabrication method thereof

Abstract

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority to and the benefit of Korean Patent Application No. 10-2010-0131906, filed in the Korean Intellectual Property Office on Dec. 21, 2010, the entire content of which is incorporated herein by reference.BACKGROUND OF THE INVENTION[0002](a) Field of the Invention[0003]The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electrical conductivity, and minimizing electrical signal delay without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.[0004](b) Description of the Related Art[0005]Electronic pac...

AI Technical Summary

Benefits of technology

[0012]The present invention has been made in an effort to provide a through silicon via (TSV) for 3D packaging of a semiconductor device and a method for manufacturing the same having advantages of easily aligning chips with high precision of submicrons or less as compared with the related art when self-aligning the substrates, bonding the semiconductor dies (or semiconductor chips) at a low temperature by using plasma, improving production process efficiency, having very high electrical conductivity, and minimizing electrical signal delay.

[0013]Further, the present invention has been made in an effort to provide a through silicon via (TSV) for 3D packaging of a semiconductor device and a method for manufacturing the same that are capable of simplifying production processes, improving productivity, and having uniform quality by sequentially bonding a plurality of semiconductor dies (semiconductor chips).

[0024]According to the exemplary embodiments of the present invention, the through silicon via (TSV) for 3D packaging of a semiconductor device and the method for manufacturing the same can easily align the chips with high precision of submicrons or less as compared with the related art when self-aligning the substrates, bond the substrates at a low temperature by using plasma, improve the production process efficiency, form very high electrical conductivity, and minimize electrical signal delay.

[0025]Further, according to the exemplary embodiments of the present invention, the through silicon via (TSV) for 3D packaging of a semiconductor device and the method for manufacturing the same can simplify the production processes, improve the productivity, and have uniform quality by sequentially bonding the plurality of semiconductor dies (or semiconductor chips).

Problems solved by technology

Wire bonding technology, which is a technology of attaching and connecting a wire to a metal pad of a connection part using an ultrasonic tool, is inexpensive in view of manufacturing costs but has a limitation in connecting fine pitches and high-density electrodes due to the bonding between the wire and the metal pad, and cannot be used for parts requiring ultrahigh speed signal processing due to an increase in parasitic inductance according to an increase in the length of the signal line for electrically connecting between the connection parts.

The solder flip chip has problems in that production cost is increased due to a very complicated connection process such as solder flux application, chip / substrate alignment, solder bump reflow, flux removal, underfill filling, curing, etc.

However, the process has a long process time in forming a film or applying or temporarily bonding the ACA material to each substrate.

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