Self-aligned polymer passivation/aluminum pad

Abstract

The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

Description

FIELD OF THE INVENTION[0001]The subject matter disclosed herein relates to methods and structures for forming self-aligned pad structures on semiconductor chip structures. More specifically, aspects of the invention relate to self-aligned polymer passivation / aluminum pad structures on semiconductor chip structures.BACKGROUND[0002]In flip chip processing of integrated circuit (IC) chips, C4 solder bumps are typically used to connect IC dies to packaging. However, due to the coefficient of thermal expansion (CTE) mismatch between different layers in the packaging, C4 solder bumps can experience large stresses which can lead to crack formation during chip joining These CTE mismatches must be managed, especially in lead free (Pb-free) solder bumps, to control cracking during chip joining (referred to as “white bump formation”).[0003]One solution for reducing stress translated in the back end of line (BEOL) process involves the use of an organic, buffering layer beneath the interconnect ...

AI Technical Summary

Benefits of technology

This patent describes a way to make a semiconductor chip structure with a layer of aluminum and a layer of polyimide. The polyimide layer is made by putting a layer of polyimide on top of a substrate and then using the aluminum layer as a mask to remove the polyimide layer from areas where it's not needed. This results in a structure where the polyimide layer is only in the areas around the aluminum layer. This method helps to reduce stress during the manufacturing process and makes it easier to connect the chip to other components.

Problems solved by technology

However, due to the coefficient of thermal expansion (CTE) mismatch between different layers in the packaging, C4 solder bumps can experience large stresses which can lead to crack formation during chip joining These CTE mismatches must be managed, especially in lead free (Pb-free) solder bumps, to control cracking during chip joining (referred to as “white bump formation”).

Unfortunately, at those thicknesses, other unintended consequences can occur, such as film formation issues, wafer warpage, and a limited ability to form the requisite small offset final via structure.

Therefore, although a thick PSPI layer can be an effective white bump risk reduction measure, the thick (and typically multi-coat) PSPI layer also drives excessive and unacceptable wafer warpage.

Also, with aluminum final metal, a blanket PSPI layer underneath can be risky, for example, because the PSPI layer can have entrapped corrosives which may outgas later and attack the Aluminum layer.

While attempts have been made to include a polyimide layer beneath an aluminum pad structure in the form of a redistribution layer (RDL), these attempts have several limitations and associated concerns.

In addition to the unmanageable level of wafer warpage that results from doing this, the thick PSPI layer in the field area of the chip gives rise to potential reliability issues because standard aluminum plasma gases or strip processes can degrade the polyimide surface, causing corrosive materials to become embedded in the polyimide.

These materials can react with the aluminum metallic pad / line sidewall, causing metal corrosion of critical features.

Also, the resist used to form the aluminum pattern may become difficult or impossible to remove cleanly, leaving debris on top of the metal pad lines.

Images