Protecting Obfuscated Circuits Against Attacks That Utilize Test Infrastructures

Abstract

A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a φ-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the φ-bit protected Obfuscation Key generated by the LFSR, and output k └φ×α┘-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Patent Application Ser. No. 62 / 721,766, filed Aug. 23, 2018, which is incorporated herein by reference in its entirety, including any figures, tables, and drawings.TECHNICAL FIELD[0002]The present application relates to semiconductor hardware data security and privacy, and in particular, the protection of intellectual property (IP) data from a design house by using a logic obfuscation technique.BACKGROUND[0003]While the globalization of the semiconductor fabrication process has accelerated innovation, lowered costs and reduced time-to-market, it has also created non-trivial trust issues among the different entities involved in integrated circuit (IC) design and fabrication. For example, due to the prohibitive cost of building and maintaining a state-of-the-art semiconductor foundry and manufacturing, most design houses have transitioned to fabless model where untrusted, off-shore fac...

AI Technical Summary

Benefits of technology

The invention provides a way to hide data during a scan of a circuit using a feedback shift register and a control module that can update the register. A dynamic obfuscation key generator generates the key based on the control vector and a shadow chain. This prevents unauthorized access to the data and ensures that only the trusted entity can know the key. The technical effects of this invention include improved security and protection of sensitive data during circuit scan.

Problems solved by technology

While the globalization of the semiconductor fabrication process has accelerated innovation, lowered costs and reduced time-to-market, it has also created non-trivial trust issues among the different entities involved in integrated circuit (IC) design and fabrication.

For example, due to the prohibitive cost of building and maintaining a state-of-the-art semiconductor foundry and manufacturing, most design houses have transitioned to fabless model where untrusted, off-shore facilities are responsible for fabricating their products.

As a result, they are now facing threats of IP theft / piracy, tampering, counterfeiting, and IC overproduction.

However, limitations and vulnerabilities of these approaches have been highlighted recently.

Even if the limitations of IEEE-P1735 standards are addressed, encrypting an RTL IP alone can never address supply chain issues like IC overproduction and tampering.

Although logic obfuscation can be an effective mechanism for establishing trust in the hardware design flow, it has not seen widespread application in semiconductor industry due to its lack of attack resiliency and formal notion of security.

For example, a recent work has shown that most logic obfuscation techniques are vulnerable to Boolean satisfiability test (SAT) based attacks.

However, it has been demonstrated that all of these SAT-resistant logic locking techniques, SARLock and Anti-SAT to name a few, possess their own critical vulnerabilities.

To be more specific, logic locking techniques that are highly resistant to SAT attacks have become more vulnerable to “bypass attacks” that can easily circumvent the effect of the SAT-resistant locking scheme.

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