ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

a technology of flash memory and oxide layer, which is applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problem of limiting the scaling down of the total physical thickness of the ono layer, and achieve the reduction of the number of e' centers and dangling bonds, and the oxygen content is high.

US6803275B1Inactive Publication Date: 2004-10-12LONGITUDE FLASH MEMORY SOLUTIONS LTD
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Patent Information

Authority / Receiving Office
US · United States
Current Assignee / Owner
Publication Date
2004-10-12
Estimated Expiration
Not applicable · inactive patent

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Abstract

Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer. In another embodiment, a process for fabricating a SONOS flash memory device includes forming a bottom oxide layer of an ONO structure on the semiconductor substrate under strongly oxidizing conditions, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.
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Description

The present invention relates to a process for preparation of a SONOS flash memory device including an ONO structure in which the bottom oxide layer exhibits reduced charge leakage. The bottom oxide layer is provided with increased oxygen content and / or reduced oxygen vacancy content.Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a singl...

Examples

first embodiment

The present invention broadly includes two embodiments. In the present invention, shown schematically in FIG. 7, a bottom oxide layer 28 is formed by a conventional process to include a first oxygen vacancy content, and is thereafter treated to reduce the oxygen vacancy content from the first oxygen vacancy content to a second oxygen vacancy content. In this embodiment, the bottom oxide layer having the second, reduced oxygen vacancy content exhibits a reduced charge leakage relative to the bottom oxide layer having the first, higher oxygen vacancy content. In one embodiment, the bottom oxide layer having the second, reduced oxygen content has a super-stoichiometric oxygen content.

second embodiment

In the present invention, shown schematically in FIG. 8, a bottom oxide layer 28 is formed by processes which include strongly oxidizing conditions, which provide the bottom oxide layer 28 with a super-stoichiometric oxygen content and thereby an oxygen vacancy content which is reduced relative to that of a bottom oxide layer made by a conventional process. In one embodiment, the bottom oxide layer 28 is formed having a substantially zero oxygen vacancy content. In one embodiment, the super-stoichiometric oxygen content provides an increased oxygen content relative to the oxygen content in a conventional bottom oxide. In one embodiment, the bottom oxide layer having the super-stoichiometric oxygen content exhibits a reduced charge leakage relative to a conventional bottom oxide layer.

The first step of both embodiments is the same. In the first step of the present invention, shown schematically in FIG. 7 as step 701 and in FIG. 8 as step 801, a semiconductor substrate is provided. Th...