Semiconductor memory device for maintaining level of signal line

Abstract

A memory array MA0 is divided into four sub memory arrays by sense amplifier strips. Word drivers belonging to each sub memory array are connected to a corresponding segment boosted signal line. A fuse is connected to each segment boosted signal line. By blowing out a fuse, the sub memory array corresponding to the blown out fuse is no longer used. The sub memory array that is no longer used is exchanged with a spare sub memory array of a spare memory array.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a circuit structure for maintaining the level of a boosted signal line and a word driver connected to the boosted signal line, and a redundancy structure.2. Description of the Background ArtFIG. 21 is a block diagram of a conventional semiconductor memory device.Referring to FIG. 21, a semiconductor memory device of a dynamic RAM includes a memory array 161, a row address buffer 164, a row decoder 163, word drivers 162a-162h, a column address buffer 167, a column decoder 166, a sense amplifier 165, an input / output circuit 168, and a control circuit 169. Memory array 161 has bit lines and word lines disposed vertically and horizontally therein. Row address buffer 164 receives an externally applied row address. Row decoder 163 receives an output of row address buffer 164. Word drivers 162a-162h respond to an o...

AI Technical Summary

Benefits of technology

Another object of the present invention is to improve the exchange efficiency of a semiconductor memory device that has exchange carried out.

According to the present aspect, in addition to the above advantage, exchange is carried at the unit of memory cell groups which are formed corresponding to a segment boosted signal line. Therefore, the exchange efficiency can be improved, and the chip area of the spare memory cell group can be reduced.

Problems solved by technology

In recent years, the circuit complexity has increased as the memory capacity becomes greater, resulting in increase of the consumed current.

This will cause increase in the chip area of the spare submemory array.

However, conventional semiconductor memory devices have problems set forth in the following.

If the potential of segment booted signal line 207a was lowered to a level in the vicinity of ground potential, the boosting up to the level of boosted potential V.sub.PP will be time consuming, resulting in a slow access time.

Therefore, the exchange efficiency is low.

Furthermore, it is difficult to increase the number of spare submemory arrays from the standpoint of the chip area.

Therefore, it was difficult to improve the yield.

There are also problems in a semiconductor memory device that carries out exchange in a word line unit as shown in FIG. 24.

When leakage occurs in a segment boosted signal line due to a defective word line, all the word lines associated with that segment boosted signal line will also become defective.

More specifically, when a switching transistor is off, the potential will become as low as the level of ground potential in the worst case due to junction leakage and subthreshold leakage.

Therefore a high speed operation could not be carried out.

In the semiconductor memory device shown in FIG. 27 where switching transistors are removed and boosted voltage V.sub.PP is supplied directly from global boosted signal line 221 to a word driver, there is a problem that the consumed current becomes so great that it causes standby current fault when current begins to leak from global boosted signal line 221 due to a fault in a word driver.

Furthermore, the output of the row decoder applied to the word driver must be completely decoded, causing increase in the circuit complexity of the row decoder.

This results in a problem that the layout pitch is reduced with respect to a row decoder.

This results in an insufficient opening of the transfer gate to cause erroneous operation.

However, the delay time by the delay means varies due to a change in the process, resulting in the possibility of an erroneous operation.

Increase in the delay time of boosted decode signal RX slows the access time.

It is extremely difficult to design the timing in which a complete self boost is carried out without delay.

However, a great potential difference is applied between the source and gate of n channel MOS transistor 181b, resulting in the possibility of the reliability of n channel MOS transistor 181b being degraded.

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