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Preparing method and application of heterobonded wafer

A hetero-bonding, wafer technology, applied in the direction of final product manufacturing, sustainable manufacturing/processing, semiconductor/solid-state device manufacturing, etc., can solve the problems of IRFPA performance degradation, lattice mismatch, indium column solder joints falling off, etc. Achieve no cross-contamination, high thermal conductivity, and easy implementation

Inactive Publication Date: 2007-10-24
EAST CHINA NORMAL UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 1. IP-ROIC adopts the method of direct reverse interconnection or indirect reverse interconnection, under the action of repeated thermal cycle load of 300-30K cycles, the three materials of indium column, GaAs substrate of detector array and silicon-based ROIC The thermal expansion coefficient (CTE) does not match, and the large stress change causes the viscoplastic deformation of the indium column, the solder joints of the indium column fall off, crack, etc., resulting in the performance degradation or even failure of the IRFPA
[0005] 2. There are two major difficulties in heteroepitaxial monolithic integration or local heteroepitaxial monolithic integration: 1) Silicon and GaAs and other III-V compound materials have a 4% lattice mismatch, resulting in high fault density

Method used

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  • Preparing method and application of heterobonded wafer
  • Preparing method and application of heterobonded wafer
  • Preparing method and application of heterobonded wafer

Examples

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Embodiment 1

[0033] Example 1 Preparation of Heterogeneous Bonded Wafer by Direct Heterogeneous Bonding at Low Temperature

[0034] The diameter of two heterogeneous wafers to be bonded is 1-8 inches. The two heterogeneous wafers to be bonded are respectively a silicon wafer prepared with ROIC and a GaAs wafer prepared with IP thin film. The smoothness of the bonding surface of the silicon wafer does not meet the bonding requirements. The bonding surface of the GaAs wafer is in the shape of a mirror surface, which has met the bonding requirements.

[0035] First put the silicon wafer into the PECVD vacuum chamber, and grow Si sequentially on the side prepared with ROIC according to the process conditions of the double-layer Damascus structure copper wiring in 0.25 μm ULSI 3 N 4 and SiO 2 The film 8. See Figure 2. Take out the silicon wafer, fix it in a special chemical mechanical planarization equipment according to the chemical mechanical planarization process of copper interconnect...

Embodiment 2

[0040] Example 2 Fabricate IRFPA of IP-ROIC with Heterogeneous Bonded Wafers

[0041] Use standard IC technology to make IP-ROIC IRFPA on heterogeneous bonded wafers: use IP standard technology to perform photolithography, dry etching, and pattern positioning on the electrode surface of heterogeneous bonded wafers to expose the lower electrode area; The ULSI standard process is used to open the lead hole; the PECVD process is used to passivate the IP quantum well side wall area; the upper electrode, the lower electrode and the lead are produced by photolithography, electron beam evaporation or sputtering process, and the IP produced by the heterogeneous bonding wafer is obtained. -IRFPA for ROIC.

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Abstract

A preparation method and an application of a hetero-bonded wafer relates to the photoelectronic component integration and application filed. Two direct linkage hetero-bonded materials at low temperature are a silicon wafer prepared for ROIC and GaAs wafer for IP films separately, first of all the surface of silicon wafer is smoothed and cleaned in terms of Cu interlink flatness technology in 0.25mum ULSI, then the GaAs wafer with the same clean and smooth surface is aligned, pre-bonded and processed under low temperature with said silicon wafer till they are bonded together directly to get the hetero-bonded material, then its thickness is reduced to 20-30mum and the rest GaAs is selected and etched with ICP high density reacting ions to the ending layer to be etched by a wet process to get the hetero-bonded wafer.

Description

technical field [0001] The present invention relates to a preparation method and application of a heterogeneous bonding wafer, to be precise, it relates to a low-temperature direct heterogeneous bonding of an infrared detector (IP) material and a silicon-based readout integrated circuit (ROIC) to prepare a heterogeneous bonding Wafer methods and applications for hetero-bonded wafers. It belongs to the technical field of optoelectronic equipment integration and application. Background technique [0002] Due to the application of infrared focal plane (IRFPA) technology in many fields such as military, environmental protection, civil, industrial and medical, the demand for large-scale IRFPA is constantly growing. However, large-scale IRFPA consists of large-scale quantum wells, HgCdTe and other types of infrared detector photosensitive elements and ROICs, which are directly or indirectly interconnected through indium columns grown separately to form a ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/00H01L31/18
CPCY02P70/50
Inventor 郭方敏甄红楼陆卫李宁于绍欣朱自强劳五一王少伟
Owner EAST CHINA NORMAL UNIV