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Semiconductor device and producing method thereof

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as poor production capacity

Inactive Publication Date: 2007-11-21
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, since the terminal 105 shown in FIG. 1 is formed on the wiring 102 by electroplating, it takes time to form the terminal 105, and the productivity of CSP formation is poor.

Method used

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  • Semiconductor device and producing method thereof
  • Semiconductor device and producing method thereof
  • Semiconductor device and producing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0037] 2 to 5 are cross-sectional views showing the steps of forming the multi-chip package (MCP) according to Embodiment 1 of the present invention.

[0038] First, as shown in FIG. 2( a ), a semiconductor wafer 1 in which first semiconductor circuits (not shown) are formed on a plurality of device regions A is prepared. As shown in the partially enlarged view of FIG. 6(a), the semiconductor wafer 1 has a protective insulating film 2 on its upper surface, and an opening 2a for exposing the first terminal (conductive pad) 3 is formed on the protective insulating film 2, and The first terminal is electrically connected to internal wiring (not shown) of the semiconductor device. The first terminal 3 is formed of aluminum, copper, or the like.

[0039] Furthermore, the semiconductor wafer 1 is, for example, a silicon wafer, and is cut into individual first semiconductor circuits in a post-process, and is divided into units of device regions A. As shown in FIG.

[0040] Next, as...

Embodiment approach 2

[0067] In Embodiment 1, after the via 11 a and the rewiring pattern 11 b are formed, the buried insulating layer 12 is formed in the via hole 10 a, and then the resin cover film 13 is formed on the resin insulating layer 10 . However, it is also possible to form the buried insulating layer 12 and the resin cover film 13 at the same time.

[0068] For example, as shown in FIG. 9( a), after a photosensitive resin film 15, such as epoxy resin, is coated simultaneously in the via hole 10a and on the resin insulating layer 10, the exposure and development resin film 15 are formed so that the third re The opening 15a through which the terminal portion of the wiring pattern 11b is exposed.

[0069] Thereafter, as shown in FIG. 9(b), the external terminals 14 are bonded to the rewiring pattern 11b through the opening 15a of the resin film 15. As shown in FIG.

[0070] According to this embodiment, the epoxy resin in the via hole 10a is used as the buried insulating layer, and the epo...

Embodiment approach 3

[0073] When the first rewiring pattern 3 is not formed on the semiconductor wafer 1 described in Embodiment 1, the following steps are employed.

[0074] First, as shown in Fig. 11(a) and (b), on the terminal 3 in the opening 2a of the protective insulating film 2 on the semiconductor wafer 1, a nickel-phosphorus coating with a thickness of 3 to 5 μm is selectively formed by electroless plating. (NiP), nickel, gold or the like as the coating conductive layer 16 .

[0075] Thereafter, as shown in FIG. 11(c), the first semiconductor device chip 5 is mounted on the semiconductor wafer 1 by the same method as in the first embodiment. As the first semiconductor device chip 5, a device having a structure in which a NiP-coated conductive film 17 is formed on the second terminal 7 of the protective insulating film 6 without forming a rewiring pattern is used.

[0076] Next, as shown in FIG. 12( a ), a resin insulating layer 10 is formed on the semiconductor wafer 1 so as to cover the...

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Abstract

A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one surface, an insulating layer (10) formed on a second semiconductor chip (1a) to cover the first semiconductor chip (5), a plurality of holes (10a) formed in the insulating layer (10) on at least a peripheral area of the first semiconductor chip (5), a via (11a) formed like a film on inner peripheral surfaces and bottom surfaces of the holes (10a) and connected electrically to the second terminal (3) of the second semiconductor chip (1a), a wiring pattern (11b) formed on an upper surface of the insulating layer (10), and an external terminal (14) formed on the wiring pattern (11b).

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having a plurality of semiconductor chips and its manufacturing method. Background technique [0002] For the next generation of portable information terminal equipment including mobile phones and mobile PCs, the improvement of miniaturization, light weight and thinness has become a primary issue. Therefore, in order to enhance the competitiveness of portable information terminals, which are expected to grow rapidly in the future, it is important to develop high-density mounting technologies that can achieve further reduction in size, weight, and thickness. [0003] As high-density mounting technologies, there are various technologies such as flip-chip mounting, multi-chip modules, and laminated substrates. Furthermore, from the need to carry multiple functions in a package, technology development of a chip-scale packag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/04H01L23/12H01L21/60H01L23/31H01L23/538H01L25/065
CPCH01L2224/16227H01L2924/01002H01L2224/73265H01L24/45H01L24/11H01L2924/01015H01L2224/48091H01L2225/06506H01L2924/01078H01L24/48H01L23/5389H01L24/16H01L2224/16H01L23/3114H01L2924/01005H01L2924/12041H01L2924/01057H01L2924/01013H01L2224/45144H01L2924/01022H01L2225/06524H01L24/97H01L25/50H01L2924/1532H01L2224/12105H01L2224/32225H01L25/0657H01L24/24H01L2225/06586H01L2224/97H01L2224/16225H01L2924/01006H01L2224/48145H01L24/94H01L2924/01028H01L2225/0651H01L2924/01079H01L2224/94H01L2924/15311H01L2924/01014H01L2224/73267H01L2924/10253H01L2224/32145H01L2924/01082H01L2224/13099H01L2225/06517H01L2224/82039H01L2924/01011H01L2924/014H01L24/82H01L2225/06541H01L2924/01029H01L2224/92244H01L2224/16145H01L2224/24226H01L2225/06513H01L2224/48227H01L2224/92H01L2924/01033H01L2224/73209H01L2224/73217H01L2924/12042H01L24/73H01L2224/05026H01L2224/05571H01L2224/05573H01L2224/05001H01L2224/05548H01L2224/056H01L2924/181H01L2224/05655H01L2224/04042H01L2224/04105H01L2224/73253H01L24/19H01L24/20H01L24/96H01L24/03H01L24/05H01L24/13H01L2224/02379H01L2224/13024H01L2224/0401H01L2224/131H01L2924/00014H01L2224/82H01L2924/00011H01L2924/00H01L2924/00012H01L2224/85H01L2224/83H01L2224/81H01L2224/05124H01L2224/05147H01L2224/03H01L2924/013H01L23/12H01L23/31H01L23/48
Inventor 松木浩久爱场喜孝佐藤光孝冈本九弘
Owner SOCIONEXT INC
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