Three-dimensional multi-gate high-voltage N type transverse double-diffused metal-oxide semiconductor device
An oxide and gate oxidation technology, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of not maximizing the use of chip area, large saturation current, small on-resistance, etc., to achieve performance improvement, The effect of good temperature characteristics and good breakdown characteristics
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Embodiment 1
[0019] A three-dimensional multi-gate high-voltage N-type lateral double-diffused metal oxide semiconductor transistor used as a high-voltage device, comprising: a P-type substrate 1, an oxide layer 2 is arranged on the P-type substrate 1, and an oxide layer is arranged on the oxide layer 2. A columnar N-type drift region 3, on the oxide layer 2 and located adjacent to both ends of the N-type drift region 3, an N-type drain 4 and an N channel 5 are respectively arranged, on the oxide layer 2 and located adjacent to the N channel 5 An N-type source 6 is provided at the position, a field oxide layer 7 is coated on the surface of the N-type drift region 3, a gate oxide layer 8 is coated on the surface of the N channel 5, and the surfaces of the field oxide layer 7 and the gate oxide layer 8 are Coated with a polysilicon layer 9, in this embodiment, a cavity 21 is provided on the oxide layer 2 and below the N-type drift region 3 and the N channel 5, and a field oxide bottom layer 7...
Embodiment 2
[0021] A preparation process for manufacturing a three-dimensional multi-gate high-voltage N-type lateral double-diffused metal oxide semiconductor tube, which is characterized in that a P-type substrate is prepared first, and then an oxide layer is prepared on the P-type substrate, and a P-type substrate is grown on the oxide layer. Silicon, perform N-type doping on a part of the P-type silicon to form an N-type drift region, grow and form a field oxide layer on both sides and the upper surface of the N-type drift region, and perform P on the other part of the P-type silicon. Type doping to form N-type channel, dry thermal oxidation growth on both sides and upper surface of N-type channel and form gate oxide layer, on both sides and upper surface of N-type channel and N-type drift region Deposit polysilicon and form a polysilicon layer on both sides and the upper surface of part of the surface. Finally, perform source and drain N-type impurity implantation, engraving holes and...
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