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Control method for raising consistence of silicon epitaxial resistivity

A control method and technology of silicon epitaxy, applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve problems such as poor resistivity consistency, improve yield, avoid self-doping effect, and simple operation.

Inactive Publication Date: 2008-04-16
HEBEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The purpose of the present invention is to overcome the above-mentioned disadvantages, in order to solve the technical problem of poor consistency of resistivity caused by self-doping of P-type silicon epitaxy, and to provide a control method for improving the consistency of resistivity of P-type silicon epitaxy

Method used

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  • Control method for raising consistence of silicon epitaxial resistivity

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Comparison scheme
Effect test

Embodiment 1

[0031] 1. Put the polished and cleaned silicon wafer into pure water with 1% hydrogen peroxide and leave it for 3 minutes to form a 5nm clean oxide layer on the surface;

[0032] 2. Put the silicon wafer into the epitaxial furnace, pass nitrogen and hydrogen in sequence according to the traditional process, and then use high-purity hydrogen chloride for in-situ polishing, raise the temperature to 1220 degrees, and use nitrogen variable flow rate to catch the gas 4 times, each time 30s, the maximum flow rate is The normal growth ventilation flow rate, the small flow rate is 1 / 10 of the normal growth ventilation flow rate, which reduces the impurity concentration in the stagnant layer by 3-6 orders of magnitude;

[0033] 3. Cool down to 1100 degrees, and grow silicon intrinsic layer with silicon source gas, with a thickness of 0.5 μm;

[0034] 4. Use nitrogen variable flow rate to inflate 4 times, each time for 30s, the large flow rate is the normal growth ventilation flow rate,...

Embodiment 2

[0040] 1. Put the polished and cleaned silicon wafer into pure water with 0.5% hydrogen peroxide for 3 minutes, and a 3nm clean oxide layer will be formed on the surface.

[0041] 2. Put the silicon wafer into the epitaxial furnace, pass nitrogen and hydrogen in sequence according to the traditional process, and then use high-purity hydrogen chloride for in-situ polishing, raise the temperature to 1230 degrees, and use nitrogen variable flow rate to catch the gas 10 times, each time 20s, the maximum flow rate is Normal growth ventilation flow rate, the minimum flow rate is 1 / 10 of the normal growth ventilation flow rate.

[0042] 3. Lower the temperature to 1150°C, and grow a silicon intrinsic layer with a thickness of 0.3 μm by passing silicon source gas.

[0043] 4. Inflate 6 times with variable flow rate of nitrogen, 20s each time, the large flow rate is the normal growth ventilation flow rate, and the small flow rate is 1 / 10 of the normal growth ventilation flow rate.

[...

Embodiment 3

[0047] 1. After the silicon wafer is polished and cleaned, soak it in pure water containing ozone for 3 minutes. The amount of ozone introduced is 50-150ml / min, and the air is ventilated for 10-15 minutes to form a 4nm clean oxide layer on the surface of the silicon wafer;

[0048] 2. Put the silicon wafer into the epitaxial furnace, pass nitrogen and hydrogen in sequence according to the traditional process, and then use high-purity hydrogen chloride for in-situ polishing, raise the temperature to 1250 degrees, and use nitrogen variable flow rate to catch the gas 6 times, each time 15s, the maximum flow rate is The normal growth ventilation flow rate, the small flow rate is 1 / 10 of the normal growth ventilation flow rate, which reduces the impurity concentration in the stagnant layer by 3-6 orders of magnitude;

[0049] 3. Lower the temperature to 1160°C, grow silicon intrinsic layer with silicon source gas, with a thickness of 0.2 μm, and seal the front and side of the graphi...

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Abstract

A method for controlling resistivety consistence of silicon epitaxy in P type includes soaking silicon water in pure water containing oxydol to form clean oxidation layer on surface of silicon water, rising air-expelling temperature up to 80-120deg.c to remove off impurities in layer and repeating this process for 4-12 times, lowing temperature quickly to be growth temperature to grow intrinsic layer for enclosing graphite base substrate totally, carrying out air-expelling process and carrying out predoping then leading in doping gas for 0.5-3min. to epitaxial system for achieving saturation of impurity concentration in epitaxial system.

Description

technical field [0001] The invention belongs to a silicon epitaxial growth process method, in particular to a control method for improving the consistency of P-type silicon epitaxial resistivity. Background technique [0002] Silicon epitaxial materials not only solve the problem of damaged layer of silicon single wafer well, can get a surface that tends to be perfect, but also can solve many problems that silicon single wafer cannot solve. For example, the degree of integration, the lifetime of minority carriers, and the speed of the circuit are improved, the leakage current of the storage unit and the soft error of alpha particles are reduced, and the power characteristics and frequency characteristics of the circuit are improved. With the further improvement of the speed and integration of IC, more stringent requirements are put forward for the quality and performance of silicon epitaxial wafers. When epitaxial growth is carried out on a heavily doped substrate, the unif...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/18
Inventor 刘玉岭檀柏梅
Owner HEBEI UNIV OF TECH