Process of making mask ROM and arrangement thereof

Abstract

A method for making mask ROM comprises the steps of, forming in sequence a grid dielectric layer and a plurality of strip-shaped conductor layer on a substrate, and forming a dielectric layer on the substrate and the first conductor layer, then patterning the dielectric layer to form a plurality of coding openings, wherein each of the coding opening exposes the first conductor layer, and forming a plurality of well regions in the first conductor layer on the bottom of the coding opening, then and forming a plurality of strip-shaped second conductor layers on the dielectric layer and in the coding opening, electrically connecting them to the well regions so as to form a diode memory element array, which can be stacked into a plurality of layers to increase the degree of integrity of the elements.

Description

technical field [0001] The present invention relates to a method for manufacturing a read-only memory (ROM), and in particular to a method for manufacturing a mask-type read-only memory (Mask ROM). Background technique [0002] Since the read-only memory has the non-volatile characteristic that the data stored therein will not be lost due to power interruption, many electrical products must have this type of memory in order to maintain the normal operation of the electrical product when it is turned on. The most basic type of read-only memory is the mask-type read-only memory. The commonly used mask-type read-only memory uses channel transistors as storage units, and selectively implants ions into The specified channel area can achieve the purpose of controlling the memory cell to be turned on (On) or turned off (Off) during the read operation by changing the threshold voltage (Threshold Voltage). [0003] As mentioned above, the memory cell array of the mask ROM is usually...

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Problems solved by technology

[0004] Since transistors have high requirements on the quality of the underlying silicon substrate and gate oxide layer, the manufacturing process conditions are relatively strict. Moreover, due to this factor, it is not easy to stack up the memory cell array composed of transistors. more than one floor

[0005] Moreover, due to factors such as leakage current, the memory cell array in the form of transistors has a small decoding margin of 0 / 1 and is not clear enough, so it is quite easy to cause decoding errors.

[0006] Moreover, since the bit line of the memory cell array in the form of a transistor is usually formed by implanting dopants in the substrate, however, its junction will become shallower as the element shrinks, which will lead to an increase in the resistance of the bit line and affect the element's performance. Operating efficiency

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