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Method for asymmetric spacer formation

A technology of spacers and sidewall layers, applied to semiconductor devices, electrical components, transistors, etc., can solve the problems of increased manufacturing costs and time-consuming

Inactive Publication Date: 2009-04-08
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This technique is time consuming and the manufacturing cost increases due to multiple masking and etching steps

Method used

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  • Method for asymmetric spacer formation
  • Method for asymmetric spacer formation
  • Method for asymmetric spacer formation

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Embodiment Construction

[0007] figure 1 8 shows the manufacturing process steps of the semiconductor device according to the embodiment of the present invention in a cross-sectional view. exist figure 1 In the illustrated manufacturing stage, a gate structure 15 and sidewall layers 10 have been formed on a substrate 12 . The gate structure 15 may comprise different layers and / or components, such as a gate oxide layer. The semiconductor substrate 12 may be a single crystal silicon substrate. Alternatively, the substrate 12 may also be a gallium arsenide substrate, a silicon-on-insulator substrate, a silicon-on-sapphire substrate or the like. The gate structure 15 is typically polysilicon or amorphous silicon, with a width that may vary by application and / or process. The sidewall layer 10 may comprise a film stack, which may include, for example, SiO 2 Silicon oxide, a nitride layer such as silicon nitride, or SiON, and can be formed using deposition techniques known in the art, eg, PECVD, LPCVD...

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Abstract

A method for asymmetric spacer formation integratable into a manufacturing process for integrated circuit semiconductor devices is presented. The method comprises forming a gate structure over a substrate, and forming a sidewall layer overlying the gate structure and substrate, wherein the sidewall layer comprises a first portion overlying a first sidewall of the gate structure. A photoresist structure is formed adjacent to the first portion, and subjected to an ion beam. The photoresist structure serves to shield at least part of the first portion from the ion beam. During irradiation, the wafer is oriented such that a non-orthogonal tilt angle exists between a path of the ion beam and a surface of the first sidewall. Formation of asymmetric spacers is possible because radiation damage to unshielded sidewall portions permits subsequent etches to proceed at a faster rate.

Description

technical field [0001] The present invention relates generally to semiconductor manufacturing processes, and more particularly to methods of forming spacers in semiconductor manufacturing processes. Background technique [0002] Asymmetric spacers serve various functions during the fabrication of semiconductor devices. For example, if a differential offset is required for different doping requirements of the source or drain regions near the gate structure, asymmetric spacers are often used to achieve this. A common technique for forming asymmetric spacers is to utilize multiple gate structure sidewall insulating layers with multiple photoresist masking and etching processes and multiple implants to create the desired offset. This technique is time consuming and the manufacturing cost is increased by the multiple masking and etching steps. [0003] Therefore, methods to overcome these problems are of utility value. Contents of the invention [0004] The present invention...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78H01L21/265H01L21/8234H01L21/8238H01L29/786
CPCH01L29/78657H01L29/66742H01L29/6678H01L21/823425H01L21/823864H01L29/78654H01L21/823468H01L21/18
Inventor M·B·富塞利耶E·E·埃里克斯S·D·雷C·温特劳布J·F·布勒
Owner GLOBALFOUNDRIES INC