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InGaAs low table face linear array or face array infrared detector chip

An infrared detector and mesa line technology, applied in the field of infrared detectors, can solve the problems of reduced device reliability, complicated diffusion process, enlarged photosensitive surface, etc., and achieve the effect of improving device reliability

Active Publication Date: 2009-09-16
SHANGHAI INST OF TECHNICAL PHYSICS - CHINESE ACAD OF SCI
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  • Application Information

AI Technical Summary

Problems solved by technology

This method can obtain an InGaAs detector with a higher detection rate, but it has some unavoidable disadvantages: the diffusion process is complicated, the photosensitive surface is enlarged, and Zn diffusion will cause a large number of defects in the InP layer, which limits the indium Performance Improvement of GaAs Detectors
The advantage of this structure is that the process is relatively simple, and the disadvantage is that the side exposure of the thicker absorbing layer introduces a large number of interface states, which limits the improvement of the device detection rate to a large extent, and poor side passivation will make the device reliable. decreased sex
In addition, it is also a difficult problem to reliably realize the extraction of ohmic contact electrodes on the p-InP cap layer

Method used

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  • InGaAs low table face linear array or face array infrared detector chip
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  • InGaAs low table face linear array or face array infrared detector chip

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Embodiment Construction

[0013] Below in conjunction with accompanying drawing and embodiment the specific embodiment of the present invention is described in further detail:

[0014] See figure 1 The epitaxial wafer used in this embodiment is an n-type InP layer 2 with a thickness of 1 μm grown sequentially on a semi-insulating InP substrate 1 with a thickness of 350 μm by MBE technology, and the carrier concentration is greater than 2×10 18 cm -3 ; In with a thickness of 2.5 μm 0.53 Ga 0.47 As intrinsic absorption layer 3; p-type InP cap layer 4 with a thickness of 0.5 μm, and a carrier concentration greater than 2×10 18 cm -3 .

[0015] figure 2 It is a schematic diagram of the cross-sectional structure of this embodiment, and the linear p-InP micro-mesas 4 are formed on the epitaxial wafer by etching. A P electrode region 6 is placed on a local area of ​​the p-InP micro-mesa, and the P electrode in ohmic contact with the p-InP is made of Au / Zn / Pt / Au, and Au, Zn, Pt, and Au are sequentially...

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Abstract

The invention discloses an InGaAs low table line array or area array infrared detector chip, comprising: forming line array or area array p-InP micro-mesas on a p-InP / InGaAs / n-InP epitaxial wafer by etching. There is an Au / Zn / Pt / Au / P electrode area in ohmic contact with the p-InP micro-mesas, and there is an etching to the n-InP layer on the side of the line or array micro-mesas and placed on the n-InP layer The common N electrode area. Except for the P and N electrode regions, the entire epitaxial wafer, including the sides, is covered with a silicon nitride passivation layer. An electrode interconnection area interconnected with the readout circuit is placed on the P electrode area, and the electrode interconnection area covers part of the micro-mesas and extends from the micro-mesas to the plane. The invention has the advantages that the reserved InGaAs layer can reduce the mesa and the side of the InGaAs layer is effectively protected. The silicon nitride passivation layer can effectively play the role of anti-reflection and reduce the surface state of the InP and InGaAs layer, and can increase the quantum efficiency of the detector and reduce the dark current. The P electrode adopts AuZnPtAu, which can form a good ohmic contact with p-InP, and Pt can effectively prevent the outdiffusion of Zn and improve the reliability of the device.

Description

technical field [0001] The invention relates to an infrared detector, in particular to a p-InP / InGaAs / n-InP (PIN) low-level line array or area array infrared detector chip. Background technique [0002] At present, PIN InGaAs detectors are mainly divided into two types: planar type and mesa type. Most planar PIN InGaAs detectors use Zn diffusion method to achieve p-type doping in the n-InP / InGaAs / n-InP cap layer InP. This method can obtain an InGaAs detector with a higher detection rate, but it has some unavoidable disadvantages: the diffusion process is complicated, the photosensitive surface is enlarged, and Zn diffusion will cause a large number of defects in the InP layer, which limit the indium GaAs detector performance enhancement. The mesa-type InGaAs detector is to etch the p-InP / InGaAs in the epitaxial material into a mesa, the cap layer p-InP is relatively thin, generally 0.1-0.5 μm, and the InGaAs absorption layer is thick, generally 1.5-3 μm . The advantage o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L31/105H01L31/0224
Inventor 唐恒敬吴小利张可锋汪洋刘向阳李永富吴家荣李雪龚海梅
Owner SHANGHAI INST OF TECHNICAL PHYSICS - CHINESE ACAD OF SCI
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