Method for manufacturing FinFET transistor

Abstract

The invention discloses a method for manufacturing a FinFET transistor. The SOI (semiconductor on insulator) wafer with a crystal orientation of (110) is selected as a substrate material, and the semiconductor layer of the SOI material is etched by an anisotropic etching method to form a side surface. A strip of semiconductor that is smooth and perpendicular to the surface, and is heavily doped in the middle of the strip. Then use the semiconductor strip as the substrate, selectively epitaxially grow a semiconductor film from both sides, and then use the sufficiently large etching selection ratio between the heavily doped and lightly doped materials to etch away the heavily doped region of the semiconductor strip, leaving the semiconductor strip The two ends and the epitaxial layer form the required ultra-thin Fin body. A gate dielectric and a gate electrode are grown on the Fin body, and then a conventional CMOS back-end process is performed to obtain a FinFET transistor.

Description

technical field [0001] The invention relates to a method of manufacturing a FinFET (Fin Field Effect Transistor). Background technique [0002] Since the invention of the integrated circuit, its performance has steadily improved. The increase in performance is mainly achieved through the continuous shrinking of the size of integrated circuit devices. Currently, the feature size of integrated circuit devices (MOSFETs) has shrunk down to the nanometer scale. At this scale, various basic and practical limitations begin to appear, making the development of integrated circuit technology based on silicon planar CMOS technology encounter unprecedented challenges. It is generally believed that after hard work, CMOS technology is still possible to advance to the 20nm or even 10nm technology node, but after the 45nm node, the traditional planar CMOS technology will be difficult to further develop, and new technologies must be produced in due course. Among the various new technologi...

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Problems solved by technology

Due to the poor uniformity and repeatability of the geometric dimensions of the formed graphics, this technology cannot be used in the production of circuits.

Although spacer image transfer technology is a simple nanoscale processing technology that can be used to make a single device, this technology will produce many parasitic patterns, so it cannot be used in the production of circuits.

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