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Method for preparing polycrystal SiGe gate nano grade CMOS integrated circuit based on multi-layer assistant structure

An auxiliary structure and integrated circuit technology, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve the problems of limited adjustment range of device threshold voltage and increased difficulty, so as to reduce process difficulty, improve manufacturing capacity, and improve performance Effect

Inactive Publication Date: 2010-01-27
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method still has a limited adjustment range for the threshold voltage of the device, and increases the difficulty of process manufacturing, making it a process bottleneck.

Method used

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  • Method for preparing polycrystal SiGe gate nano grade CMOS integrated circuit based on multi-layer assistant structure
  • Method for preparing polycrystal SiGe gate nano grade CMOS integrated circuit based on multi-layer assistant structure
  • Method for preparing polycrystal SiGe gate nano grade CMOS integrated circuit based on multi-layer assistant structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] Embodiment 1: Prepare a CMOS integrated circuit with a polycrystalline SiGe gate with a 75nm conductive channel on a Si substrate. The specific steps are as follows:

[0033] Step 1, deposit a masking layer, such as figure 2 (a) Shown.

[0034] (1a) Select the crystal orientation as , The doping concentration is 10 15 cm -3 Left and right p-type Si substrate sheet 1;

[0035] (1b) Thermally oxidize a layer of 25nm thick SiO on the substrate 2 Buffer layer 2;

[0036] (1c) In SiO 2 A 120nm thick SiN layer 3 is deposited on the buffer layer by plasma enhanced chemical vapor deposition PECVD method, which is used for the masking of the well region implantation.

[0037] Step 2, forming a well region, such as figure 2 (b) Shown.

[0038] (2a) Photoetching the P-well region 4 and the N-well region 5 on the SiN layer 3 in the order of phases;

[0039] (2b) Boron is implanted in the P-well region to form a p-type region, and the surface of the P-well region is thermally oxidized to f...

Embodiment 2

[0068] Embodiment 2: Prepare a CMOS integrated circuit with a polycrystalline SiGe gate with a 65nm conduction channel on an SOI substrate. The specific steps are as follows:

[0069] Step 1, deposit a masking layer, such as figure 2 (a) Shown.

[0070] (1a) Select the crystal orientation as , The doping concentration is 10 15 cm -3 Left and right p-type SOI substrate sheet 1;

[0071] (1b) Thermal oxidation of a layer of 15nm thick SiO on the substrate 2 Buffer layer 2;

[0072] (1c) In SiO 2 A 100nm thick SiN layer 3 is deposited on the buffer layer by atmospheric chemical vapor deposition APCVD method, which is used for the masking of the well region implantation.

[0073] Step 2, forming a well region, such as figure 2 (b) Shown.

[0074] (2a) Photoetching the P-well region 4 and the N-well region 5 on the SiN layer 3 in the order of phases;

[0075] (2b) Boron is implanted in the P-well region to form a p-type region, and the surface of the P-well region is thermally oxidized to...

Embodiment 3

[0104] Embodiment 3: Prepare a CMOS integrated circuit with a polycrystalline SiGe gate with a 90nm conductive channel on a Si substrate. The specific steps are as follows:

[0105] Step 1, deposit a masking layer, such as figure 2 (a) Shown.

[0106] (1a) Select the crystal orientation as , The doping concentration is 10 15 cm -3 Left and right p-type Si substrate sheet 1;

[0107] (1b) Thermally oxidize a layer of 35nm thick SiO on the substrate 2 Buffer layer 2;

[0108] (1c) In SiO 2 A 130nm thick SiN layer 3 is deposited on the buffer layer by low-pressure chemical vapor deposition LPCVD method, which is used for masking the well region implantation.

[0109] Step 2, forming a well region, such as figure 2 (b) Shown.

[0110] (2a) Photoetching the P-well region 4 and the N-well region 5 on the SiN layer 3 in the order of phases;

[0111] (2b) Boron is implanted in the P-well region to form a p-type region, and the surface of the P-well region is thermally oxidized to form SiO 2 ...

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Abstract

The invention discloses a method for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid and is based on a multi-layer assistant structure. The method includes the following steps: fabricating an N / P well and growing a Poly-SiGe / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer on the surface, except the SiN at the side of the window; etching the SiN on the surface of the substrate; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN; based on the etching ratio of SiO2 to SiN(4:1) and the etching ratio of Poly-SiGe to SiN, etching the SiO2 and Poly-SiGe on the surface except on the side wall of the SiN so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The invention can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nano-scale Si integrated circuits by using the existing micro-scale Si integrated circuit manufacturing process. Background technique [0002] Nowadays, information technology has become the core technology of the national economy. It serves various fields of the national economy. Microelectronics technology is the key to information technology, and integrated circuits are even more important. Since its inception in 1958, integrated circuits have developed at an alarming rate and have become the core of information science and technology and the cornerstone of national economic development and national defense construction. They have had a huge impact on world politics, economy and culture. As the fastest growing, most influential, and most widely used technology in human history, integrated circuits have become an impor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 张鹤鸣戴显英舒斌宣荣喜胡辉勇宋建军王冠宇徐小波屈江涛
Owner XIDIAN UNIV
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