Flash- and rom-memory

Abstract

The present invention provides a method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

Description

technical field [0001] The present invention relates to a method for converting flash memory to read-only (ROM) memory. Furthermore, the present invention relates to a semiconductor device including the thus converted ROM memory. Background technique [0002] In current ULSI technology, many semiconductor devices are fabricated as "system-on-chip" (SOC) devices. In such a system-on-chip, initially separately fabricated device structures are combined on a single chip. This allows the incorporation of eg analog, bipolar, (non-volatile) memory and logic CMOS technologies on a small semiconductor area. [0003] Often, the mainstream process of a baseline technology is extended to embed one or more other technologies as an option. Typically, the baseline technology involves CMOS technology, which requires single-level polysilicon fabrication technology. Other technologies requiring multi-layer polysilicon fabrication techniques, such as analog, bipolar and (non-volatile) memo...

AI Technical Summary

Problems solved by technology

This may adversely affect the magnitude of the bit line current and peripheral circuits

[0013] More generally, the prior art approach has the disadvantage of requiring modifications to the SOC device fabrication process at a relatively early stage in the process flow

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