Semiconductor device and its manufacturing method

Abstract

The invention discloses a manufacturing method for a semiconductor device, including the following steps that: a grid electrode with a sidewall spacer is formed on a semiconductor substrate; the sidewall spacer comprises a silicon oxide layer and a silicon nitride layer; a source region and a drain region are formed inside the semiconductor substrate; moreover, metal silicides are formed on the surfaces of the grid electrode, the source region and the drain region; the silicon nitride layer arranged inside the sidewall spacer is removed; an etching stop layer is formed on the surface of the substrate comprising the grid electrode, the source region and the drain region; moreover, a medium layer is deposited on the surface of the etching stop layer. The invention can improve the filling quality of a PMD layer in the space between grid electrodes.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a complementary metal oxide semiconductor device (CMOS) and a manufacturing method thereof. Background technique [0002] With the rapid development of semiconductor device manufacturing technology, the density of devices in integrated circuits is getting higher and higher, and the critical dimensions of devices have reached the deep submicron stage. In this case, new challenges are presented for the space filling process between components. figure 1 A schematic diagram illustrating an existing semiconductor device and its formation process. Such as figure 1 As shown, at the beginning of the back end of line (BEOL) forming the interconnection layer, it is usually necessary to combine the MOS transistors formed in the front end of line (FEOL) with the lowest layer of the interconnection layer A dielectric layer 20 is deposited between the 18, and the dielect...

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Problems solved by technology

Since the PMD layer 20 needs to fill the space between the grid electrodes 14 and 12 without gaps, the deposition effect of the PMD layer 20 affects the formation quality of the follow-up contact hole 16

When the manufacturing process enters the process node below 90nm, the space distance between the gates 12 and 14 is very narrow, similar to a high aspect ratio trench. In this case, it becomes more and more difficult to fill the space between the gates 12 and 14. difficulty

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