Semiconductor device has conductive projection and its manufacturing method

Abstract

The invention discloses a semiconductor device with a conductive lug and a method for preparing the same, wherein the method mainly is that: a first metal layer electrically connected with the welding pad is formed on a semiconductor base material with a welding pad and a protective layer and is covered with and partially exposed from a second covering layer; and a second metal layer which is in electric connection with the first metal layer form the exposed part is formed on the second covering layer, and is covered with and is exposed partially from an opening of a third covering layer, and a conductive bump having a metal column and a soldering tin material is formed on the second metal layer in the opening accordingly, thereby providing a buffer effect by means of the covering layers and the metal layers and avoiding the problem of layer separation because the prior under bump metallurgy of a welding block formed on the welding pad directly withstands the stress transmitted by the metal column.

Description

technical field [0001] The invention relates to a semiconductor device and its manufacturing method, in particular to a semiconductor device with conductive bumps and its manufacturing method. Background technique [0002] The traditional flip-chip (Flip Chip) semiconductor packaging technology is mainly to form solder bumps (Solder Bump) on the pads of the chip, and then directly electrically connect with the carrier such as the substrate (Substrate) through the solder bumps. In terms of wire bonding, flip-chip technology has a shorter circuit path and better electrical quality. At the same time, it can be designed in the form of an exposed crystal back, which can also improve chip heat dissipation. [0003] Before forming solder bumps on the chip with the flip-chip technology, it is necessary to form the Under Bump Metallurgy (UBM) on the chip pads as disclosed in US Patent Nos. 6,111,321, 6,107,180, and 6,586,323. , so that the solder bumps can be firmly adhered to the c...

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Problems solved by technology

[0005] Although the aforementioned conductive bumps with relatively high height copper pillars can absorb large thermal stress (thermal stress) when the thermal expansion coefficient difference between the chip and the substrate is large, but when applied to a chip with a larger size, such as 15*15mm In the above, for the conductive bumps containing copper pillars formed at the corners of the chip, because the thermal stress it receives is farther away from the center of the chip, the thermal stress it bears is relatively greater, which leads to the metal layer at the bottom of the solder bump It is still unable to effectively absorb the stress transmitted by the copper pillar, and the cracking and delamination C problems of the metal layer at the bottom of the solder block are still very easy to occur here, such as Figure 1B shown

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