A self-adapted tolerance method based on learning for chip network

Abstract

A self-adapting error-tolerant method which is used for on-chip network and is based on studying belongs to the field of the on-chip interconnection network. The invention is characterized in that the transmitting and receiving ends are respectively provided with a transmitting module and a receiving module. In the transmitting module, according to the known sequence which is transmitted to each path of the on-chip network by the error-tolerant method selector and the received sequence, an error probability p of each path channel and an error probability q which can not be corrected by the error correction code when error exists are calculated out. To the data inputted by the intelligent IP block, the error retransmission method and mixed fault-tolerant method is determined by firstly encoding with the error detecting code encoder and then comparing the magnitude of p and kd-kh/kd-kh*q thereby determining whether the data should be transmitted to the error detecting code encoder. The procedures are opposite at the receiving end, whether the data should be transmitted to the error detecting code encoder is determined according to the error-tolerant flag bit in the data package, and then the data package is executed with error detection through the error detecting code decoder for determining whether the data package needs retransmission. The invention increases the throughput of the on-chip network and reduces the transmission delay and communication power consumption.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the field of on-chip interconnection network design. Background technique [0002] Integrated circuits have been advancing in accordance with Moore's Law. The number of intelligent IP (Intellectual Property) blocks integrated into a single chip is increasing. The traditional bus-based on-chip interconnection structure has already performed well in terms of bandwidth, power consumption, reliability, and scalability. With more and more limitations, on-chip communication has replaced computation as the bottleneck of integrated circuit design. Network-on-Chip (NoC), as a key technology in the field of integrated circuit design, is used to solve the problem of on-chip interconnection caused by the increase in chip size. [0003] With the development of the technology, the power supply voltage of the chip and the threshold value of the transistor are getting lower and lower, a...

AI Technical Summary

Problems solved by technology

Moreover, for a formed on-chip network, different paths often have different error conditions. If a single fault-tolerant solution is adopted, the performance of some paths will deteriorate

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