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Production method for low-conducting impedance power field effect pipe VDMOS

A technology of power field effect transistor and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increased on-resistance, etc., and achieve the effect of reducing on-resistance and high doping concentration

Active Publication Date: 2009-02-18
SHANXI YONGCHANG TECH
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Problems solved by technology

In order to achieve high voltage, the doping concentration of the epitaxial layer must be reduced, but this will cause an increase in on-resistance. Therefore, there is a contradiction between breakdown voltage and on-resistance in power MOS devices.

Method used

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  • Production method for low-conducting impedance power field effect pipe VDMOS
  • Production method for low-conducting impedance power field effect pipe VDMOS
  • Production method for low-conducting impedance power field effect pipe VDMOS

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Embodiment Construction

[0017] The manufacturing method of the low conduction resistance power field effect transistor VDMOS of the present invention, its preferred embodiment is, comprises

[0018] Step 1, growing an epitaxial layer on a silicon base layer, the silicon base layer can be an N-type silicon base layer, and the epitaxial layer is an N-type epitaxial layer; it can be an N-type silicon base layer, and the epitaxial layer is an N-type epitaxial layer Floor.

[0019] Take the N-type silicon base layer as an example:

[0020] Step 2. Growing a field oxide layer on the epitaxial layer: first perform dry oxidation on the epitaxial layer, then perform wet oxidation, and then perform dry oxidation. The thickness of the final field oxide layer is 9000-11000A, generally 10000A about.

[0021] The process temperature range of the growth field oxide layer is 750°C-1100°C.

[0022] Firstly, from low temperature to high temperature, the heating time is about 96 minutes, which can be 86-106 minutes,...

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Abstract

The invention discloses a method for manufacturing a field effect tube VDMOS with low conduction impedance power, which comprises A. growing an epitaxial layer on a silicone base layer; B. growing a field oxide layer on the epitaxial layer; C. performing ion injection to the epitaxial layer; D. sedimenting a grate oxide layer and a polycrystalline silicon layer. After growing the field oxide layer on the epitaxial layer, a process for performing ion injection to the epitaxial layer is provided, which not only can reduce doping concentration of the epitaxial layer to realize high breakdown voltage, but also can reduce conduction impedance.

Description

technical field [0001] The invention relates to a semiconductor processing technology, in particular to a manufacturing method of a low conduction resistance power field effect transistor VDMOS. Background technique [0002] At present, MOS (power field-effect transistor), especially VDMOS (vertical double-diffused power field-effect transistor) devices have a series of unique characteristics such as large input impedance, high switching speed, voltage control, and good thermal stability. It has been widely used in stabilized power supply, high frequency heating, computer interface circuit and power amplifier. [0003] For MOS power devices such as VDMOS, obtaining sufficiently high BVPT (drain-source breakdown voltage) and as low as possible Ron (on-resistance) are two main aspects that need to be considered in the design at the same time. For MOS devices with high withstand voltage, Ron is mainly determined by the resistance of the epitaxial region. The thicker the epita...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/265
Inventor 姜岩峰
Owner SHANXI YONGCHANG TECH
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