Ultrahigh-speed comparator with low offset

Abstract

The invention provides an ultrahigh-speed comparator with low offset, and belongs to the technical field of composite signal integrated circuits. The comparator comprises a preamplification circuit, adynamic latch circuit and an output latch circuit which hare connected in sequence, wherein, the preamplification circuit comprises a fully differential input structure with a positive resistor and anegative resistor serially connected as load and is used for amplifying difference value between input signals and reference signals; the dynamic latch circuit is equipped with a bistable structure which is connected from head to tail by an inverter, and used for amplifying the output signals of the preamplification circuit and establishing preceding stage output to digital logic output level; and the output latch circuit is composed of two cross-coupled NMOS transistors and PMOS common source amplification input, and used for outputting preceding stage output in a latch time, and keeping output result of the dynamic latch circuit at high impedance state in a reset stage so as to reduce input offset voltage of the comparator, increase speed of the comparator and well meet requirements ofhigh-speed analog-to-digital converter design.

Description

technical field [0001] The invention relates to the technical field of mixed-signal integrated circuits, in particular to a low offset ultra-high-speed comparator. Background technique [0002] With the development of modern communication technology and signal processing technology, more and more analog signals need to be converted into digital signals for processing, so higher requirements are put forward for high-speed and high-precision analog-to-digital converters (ADC). But in ultra-high-speed analog-to-digital converters, the design of high-speed and high-precision comparators is the difficulty and bottleneck of the entire design. [0003] The structure of the existing high-speed comparator includes: a multi-level open-loop comparator, a latch comparator, a dynamic latch comparator and a pre-amplified latch comparator. Among them, the multi-level open-loop comparator is easy to achieve high speed and high precision. However, due to the limitation of the bandwidth of t...

AI Technical Summary

Problems solved by technology

Among them, the multi-stage open-loop comparator is easy to achieve high speed and high precision. However, due to the limitation of the bandwidth of the operational amplifier, the speed of this type of comparator is difficult to reach Gsps (megabits per second), so the general ultra-high-speed comparator The comparator adopts the structure of latching comparator to meet the requirement of speed

[0004] In the process of realizing the present invention, it is found that there are at least the following problems in the prior art: the general CMOS (Complementary Metal Oxide Semiconductor) latch comparator has a large offset voltage (even reaches 50mV sometimes), which seriously affects the comparator The accuracy limits the application of CMOS latch comparators in high-speed high-precision analog-to-digital converters

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