Method for reducing gate induced drain leakage current in N-channel metal oxide semiconductor (NMOS) devices

Abstract

The invention relates to a method for reducing gate induced drain leakage in NMOS devices. The lightly doped drain injection technology of the NMOS devices includes the following steps: a primary N type lightly doped ion implantation is carried out in primary energy and primary dosage; a secondary N type lightly doped ion implantation is carried out in secondary energy and secondary dosage; wherein, the foreign ion injected in the primary lightly doped ion implantation and the foreign ion injected in the secondary lightly doped ion implantation are elements in the same group, and the diffusion coefficient of the foreign ion injected in the secondary ion implantation is larger than or equal to that of the foreign ion injected in the primary ion implantation; and the energy value of the secondary energy is larger than that of the primary energy and the dosage value of the secondary dosage is smaller than that of the primary dosage. The invention can improve gate induced drain leakage current effect of the NMOS devices without inducing leakage current of PN junction between NLDD doped region and pocket doped region.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for reducing gate-induced drain leakage (Gate Induced Drain Leakage, GIDL) of an N-type metal oxide semiconductor (NMOS) device. Background technique [0002] Metal-oxide-semiconductor devices are widely used due to their advantages such as low power consumption and fast response. A typical MOS device includes a gate, a source, and a drain. In order to avoid or suppress the leakage current between the source and the drain caused by the shortening of the conductive channel length, the industry introduces a lightly doped drain when manufacturing metal oxide semiconductor devices. A Light Doped Drain (LDD) implantation process is used to form an LDD doped region in a MOS device. For example, in the Chinese patent application document with publication number CN 1143830A, a method for manufacturing a MOS transistor with an LDD structure is disclosed. [0...

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Problems solved by technology

[0003] With the advancement of semiconductor manufacturing technology, the size of metal oxide semiconductor devices is also decreasing, and the GIDL effect is more serious, especially for high threshold voltage metal oxide semiconductor devices. The GIDL effect is more obvious. By adjusting the metal oxide semiconductor device In the LDD process of the manufacturing process, although the formation of a shallow junction LDD doped region can improve the GIDL effect to a certain extent, it will cause a PN junction between the LDD doped region and the pocket doped region (Pocketimplant) in the semiconductor substrate. leakage current

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