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Grid and formation method thereof

A gate, gate dielectric layer technology, applied in electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve problems such as complicated operations, achieve electrical and reliability improvements, enhance reliability, and improve device performance. Effect

Active Publication Date: 2011-03-23
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] To sum up, in the traditional process, in order to improve the electrical performance of CMOS devices and enhance their reliability, it is necessary to perform multi-step process improvement, and the operation is complicated.

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Embodiment Construction

[0028] Although the invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it should be understood that those skilled in the art can modify the invention described herein and still achieve the advantageous effects of the invention. Therefore, the following description should be understood as a broad instruction for those skilled in the art, rather than as a limitation of the present invention.

[0029] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with sy...

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Abstract

The invention provides a grid formation method, comprising the following steps: forming a gate dielectric layer on a substrate; forming a polysilicon layer on the gate dielectric layer; doping the polysilicon layer with boron ion and fluorineion; schematizing the doped polysilicon layer to form the grid. Reliability can be strengthened in the process of improving the electric performance of CMOS device. The grid is formed on the gate dielectric layer, and boron ions and fluorine ion are formed in the grid, thus ensuring that the CMOS device which contains the grid has improved electric performance and reliability.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a gate and a forming method thereof. Background technique [0002] Complementary metal oxide semiconductor (CMOS) devices, such as metal oxide semiconductor field effect transistors (MOSFETs), are commonly used in ultra large scale integration (ULSI) fabrication processes. How to improve the electrical performance of CMOS devices (such as reducing the demand for power consumption) is a constant pursuit of process development. [0003] In order to improve the electrical performance of CMOS devices, many attempts have been made in the industry, such as provided in the Chinese patent application with the publication number "CN 1610065A" published on April 27, 2005. In practice, usually through the The polysilicon gate layer performs a pre-doping operation to implant n-type impurities (such as phosphorus), or performs a pre-doping operation on the polysilicon gat...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/265H01L21/336H01L29/49H01L29/78
Inventor 居建华
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP