Method for forming shallow trench isolation structure and method for manufacturing semiconductor device

Abstract

The invention discloses a manufacturing method for forming a shallow trench isolation structure and a method for manufacturing a semiconductor device. The method for forming the shallow trench isolation structure comprises the steps of: providing a silicon wafer; forming a semiconductor substrate on the silicon wafer; etching the semiconductor substrate, and forming at least 100 trenches which aresymmetrically distributed around the center of the silicon wafer in the semiconductor substrate of a central region and an edge region of the silicon wafer; forming side walls and bottom surface padoxide layers which cover the trenches in the trenches, wherein the thicknesses of the pad oxide layers formed in the trenches of the edge region of the silicon wafer are greater than those of the padoxide layers formed in the trenches of the central region of the silicon wafer; and filling oxide on the pad oxide layers in the trenches to ensure that the surfaces of the oxide in the trenches and the surface of the semiconductor substrate are on the same plane. The methods improve the deformation phenomenon of the silicon wafer, and ensure that the deformation of the silicon wafer is reduced, thereby improving the utilization rate of the edge region of the silicon wafer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a shallow trench isolation structure and a manufacturing method for a semiconductor device. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the integrated circuit manufacturing process has developed from a few interconnected devices on a single silicon chip to millions of devices. Conventional integrated circuits have provided performance and complexity far beyond what was originally envisioned, and to achieve improvements in complexity and circuit density, device features have shrunk. [0003] With the shrinking of the feature size of the device, the accuracy of device manufacturing is required to be higher and higher, which brings new challenges to the device manufacturing process. Publication number: CN101154617A, titled: in the Chinese patent application of the manufacturing method o...

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Problems solved by technology

[0004] However, the problem with the above-mentioned method is that in production, mass production is usually carried out, that is, multiple identical semiconductor devices, such as MOS devices, are produced on a silicon wafer at the same time.

Figure 4 and Figure 5 It can be seen that in the MOS device on the edge of the silicon wafer, the active region 103 is not symmetrically distributed on both sides of the gate 112, that is, there is a gate misalignment phenomenon, which makes the electrical performance of the device poor, and even makes the silicon wafer The devices in the edge area are unqualified, which results in waste of the edge area of ​​the silicon wafer

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