Vertical double-diffusion MOS transistor structure

Abstract

The invention provides a vertical double-diffusion MOS transistor structure and belongs to the field of semiconductor devices. The vertical double-diffusion MOS transistor structure comprises a semiconductor substrate, an epitaxial layer, a source doped area, a channel area, a gate oxide layer and a polysilicon gate; moreover, a thick insulating layer is arranged between the polysilicon gate and the epitaxial layer at positions beside the channel area in a horizontal direction; and due to the introduction of the insulating layer, the relative distance between the polysilicon gate and the epitaxial layer is increased, namely the distance between two polar plates of a gate-drain capacitor is increased, so that under conditions of not changing the area of the polysilicon gate and not increasing the on resistance of the device, the gate-drain capacitor of the device is effectively reduced, the electrical charging-discharging time of the gate-drain capacitor in a process of opening or closing the MOS transistor is greatly shortened, the opening-closing speed of the MOS transistor is improved, the dynamic loss of the MOS transistor is lowered, and the performance of the device is greatly improved.

Description

technical field [0001] The invention relates to a MOS transistor structure, in particular to a double-diffused MOS transistor structure with a vertical structure, and belongs to the field of semiconductor devices. Background technique [0002] In semiconductor integrated circuits, the circuit based on double-diffused MOS transistors, referred to as DMOS, uses the difference in lateral diffusion speed of two impurity atoms to form a self-aligned sub-micron channel, which can achieve high operating frequency and speed. The DMOS transistors can be divided into two types: lateral DMOS transistors (LDMOS for short) and vertical DMOS transistors (VDMOS). Among them, vertical DMOS transistors are increasingly used in the field of semiconductor integrated circuits due to their good performance and high integration. [0003] Figure 1a It is a schematic cross-sectional structure diagram of a traditional vertical double-diffused MOS transistor (VDMOS for short) 100 . Such as Figur...

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Problems solved by technology

[0006] In the prior art, there are generally two ways to reduce the gate-drain capacitance Cgd of a MOS transistor: one way is to reduce the area of ​​the gate and the drain, but this method will bring a larger on-resistance Rds(on ), while increasing the switching loss, it will also cause a decrease in device current, voltage and other performance; another method is to reduce the relative contact area between the gate and the drain, usually using a certain method for the gate Shielding technology, thereby reducing the relative capacitance of the gate-drain, in the Chinese patent CN03817927.X, a semiconductor gate structure including a shielding electrode and a switch electrode is provided, although this structure reduces the gate-drain to a certain extent. Relative capacitance, but the structure involves more process steps, and the preparation method is more complicated, which increases the manufacturing cost of the MOS transistor. In addition, the structure involves multiple dielectric layers, and its dimensional accuracy is not easy to control, which affects other properties of the MOS transistor and MOS The mutual integration between devices has a certain influence

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