The invention relates to a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) transistor, belonging to the field of semiconductor devices. The VDMOS transistor comprises a semiconductor substrate, an epitaxial layer, a source doping region, a channel region, a gate oxide layer and a polysilicon gate, and an insulation dielectric layer with a thickness larger than that of the gate oxide layer is deposited at the side of the channel region between the polysilicon gate and the gate oxide layer in a horizontal direction through PECVD (Plasma Enhanced Chemical Vapor Deposition) process. By introducing the insulation dielectric layer, the relative distance between the polysilicon gate and the epitaxial layer is increased, namely the distance between the two polar plates of the gate-drain capacitance of the device is increased, thus under the condition that the area of the polysilicon gate is not changed and the on-resistance of the device is not increased, the gate-drain capacitance of the device is effectively reduced; the charging and discharging time for the gate-drain capacitance during the switching of the MOS (Metal Oxide Semiconductor) transistor is greatly reduced, the switching speed of the MOS transistor is increased, the dynamic loss is reduced, and therefore the performance of the device is greatly improved.