Method for preparing vertical double-diffusion MOS transistor

Abstract

The invention relates to a method for preparing a vertical double-diffusion MOS transistor, which comprises the following steps: firstly, simultaneously growing thick insulating layers at a position beside a channel region on the surface of an epitaxial layer in the horizontal direction and on a buffering isolation oxide layer of a device layer at the position; and secondly, finishing the preparations of a source electrode, a drain electrode and a grid electrode of the vertical double-diffusion MOS transistor by adopting a conventional process method. The introduction of the thick insulating layers increases the relative distance between a polysilicon gate and the epitaxial layer, namely increases the distance two pole plates of a grate-drain capacitor, so under the condition of not changing the polysilicon grate area and not increasing the on-resistance of a device, the method effectively reduces the grate-drain capacitance of the device, greatly shortens the time for charging and discharging the grate-drain capacitor in the switching process of the MOS transistor, improves the switching speed of the MOS transistor, reduces the dynamic loss of the MOS transistor, and greatly improves the performance of the device.

Description

technical field [0001] The invention relates to a method for preparing a MOS device, in particular to a method for preparing a double-diffusion MOS transistor with a vertical structure, and belongs to the technical field of semiconductors. Background technique [0002] In semiconductor integrated circuits, the circuit based on double-diffused MOS transistors, referred to as DMOS, uses the difference in lateral diffusion speed of two impurity atoms to form a self-aligned sub-micron channel, which can achieve high operating frequency and speed. The DMOS transistors can be divided into two types: lateral DMOS transistors (LDMOS for short) and vertical DMOS transistors (VDMOS). Among them, vertical DMOS transistors are increasingly used in the field of semiconductor integrated circuits due to their good performance and high integration. [0003] Figure 1a It is a schematic cross-sectional structure diagram of a traditional vertical double-diffused MOS transistor (VDMOS for sh...

AI Technical Summary

Problems solved by technology

This method involves many process steps such as the deposition of the dielectric layer, ion implantation, and annealing, and requires high process precision, which requires strict control of process costs. In addition, according to the structural characteristics of CMOS devices, this method is only applicable to source, gate, etc. For the vertical double-diffused MOS transistor structure whose source / gate and drain are located on both sides of the semiconductor substrate, this method has limited improvement on Miller capacitance.

Images