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Caching collaboration system of on-chip multi-core processor and cooperative processing method thereof

A multi-core processor and high-speed cache technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as performance impact, uncoordinated policy control and management, and complexity, and achieve low average memory access latency and low average Memory access delay and failure rate, the effect of reducing hardware overhead

Inactive Publication Date: 2010-05-12
SUZHOU INST FOR ADVANCED STUDY USTC
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  • Description
  • Claims
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Problems solved by technology

[0007] The purpose of the present invention is to provide an on-chip multi-core processor high-speed cache cooperation system, which solves the problem that the traditional cooperation Cache in the prior art does not effectively control and manage the cooperation strategy, resulting in increasingly complex load types and increasing working set scale. Issues such as large cases that negatively impact performance

Method used

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  • Caching collaboration system of on-chip multi-core processor and cooperative processing method thereof
  • Caching collaboration system of on-chip multi-core processor and cooperative processing method thereof
  • Caching collaboration system of on-chip multi-core processor and cooperative processing method thereof

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Embodiment

[0036] In this embodiment, the cooperative Cache on the multi-core processor is realized by using the simulation method technology. The multi-core simulator based on Simplescalar is used, and the relevant configuration parameters of the components are shown in Table 1. The hardware structure of the on-chip multi-core processor implemented by this configuration is as follows figure 1 shown.

[0037] Table 1 Simulator related configuration parameters

[0038]

[0039]

[0040] Each processor core of the on-chip multi-core processor has a private first-level instruction and data cache, and also has a private second-level cache body. The first-level cache and the second-level cache are strictly contained. Each processor core has a missing queue (MissQ), which accepts and processes data access requests or consistency requests of each processor core and accesses the secondary Cache or router, which handles local or remote requests; each processing The core has a write-back q...

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Abstract

The invention discloses a cache cooperative system of an on-chip multi-core processor and a cooperative processing method thereof. The system comprises a memory and an on-chip multi-core processor coupled with the memory, and is characterized in that each processor core of the multi-core processor comprises a private L1 cache and a private L2 cache which has strict inclusion relation with the private L1 cache; all the processor cores of the multi-core processor share a centralized consistent catalog which is used for realizing consistent strategy in the L1 cache, the L2 cache and the memory. The cooperative cache system has the advantages of small hardware expense, good expandability and large system throughput and the like.

Description

technical field [0001] The invention belongs to the technical field of storage of processors of information processing systems, and in particular relates to a high-speed cache cooperation system of on-chip multi-core processors and a cooperation processing method thereof. Background technique [0002] With the development of integrated circuit technology to the nanometer level, the shrinking process size meets the development of chip miniaturization, high speed and higher integration. On-chip multi-core processor (ChipMulti-Processor, CMP) is an architectural design that appeared in the 1990s. It was originally proposed by researchers at Stanford University in the United States. Processor cores, and develop instruction-level, thread-level and other levels of parallelism through multi-core parallel execution to improve performance. In an on-chip multi-core processor environment, multiple cores run simultaneously and compete to access storage resources such as the limited Cac...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F15/167G06F12/0817G06F12/084G06F12/0897
Inventor 吴俊敏赵小雨隋秀峰
Owner SUZHOU INST FOR ADVANCED STUDY USTC
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