Test circuit for predicting static discharge failure of integrated circuit and prediction method thereof

Abstract

The invention discloses a test circuit for predicting static discharge failure of an integrated circuit and a prediction method thereof. The prediction method comprises the following steps of: measuring the declination of an MOS (Metal-Oxide Semiconductor) device under ESD (Electro-Static Discharge) stress in the integrated circuit by utilizing the degradation of failure testing capacitors (8 and9) under the action of the ESD stress; coupling the undischarged ESD stress of an ESD protection circuit onto the failure testing capacitors (8 and 9) by utilizing a static discharge stress coupled circuit comprising diodes (3 and 4); meanwhile, after the ESD stress is detected by a stress and delay controller circuit, generating a control signal, transmitting the control signal to a stress control circuit (12), starting a boost circuit comprising diodes (5 and 6), a switching circuit (11) and a boost capacitor (10) and generating a high-stress voltage to accelerate the declination of the failure testing capacitors (8 and 9), and if the failure testing capacitors (8 and 9) fail, outputting a failure signal by a comparator (14) to predict that the integrated circuit is about to fail, and realizing real-time prediction. The invention can be used for predicting the static discharge failure of the integrated circuit.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and relates to an electrostatic discharge failure real-time prediction circuit and a prediction method, which can be used for testing and life prediction of large / ultra large scale integrated circuits. Background technique [0002] At present, the reliability testing technology of integrated circuits has been more and more widely used and developed, such as aerospace electronics, avionics, automotive electronics and other fields. With the development of integrated circuits, the system-on-chip (SOC), including the central processing unit, memory, and peripheral circuits, has a great effect on improving system performance, reducing system energy consumption, reducing system electromagnetic interference, and improving system integration. Helping, it not only conforms to the trend of light and thin products, but also has high-efficiency integration performance, so it is replacing the main...

AI Technical Summary

Problems solved by technology

[0003] When there is electrostatic discharge ESD stress at the SOC port, for the failure of the SOC internal circuit caused by the ESD stress that is not completely discharged by the protection circuit, the previous test is a process control test applied in production and a specially designed on-wafer The failure test circuit performs failure test. Since this test uses a specially designed failure test circuit on the wafer, it can only test the SOC failure caused by electrostatic discharge in a simulated SOC working environment, and this test cannot be used for ESD. Real-time test and failure alarm for the failure caused by the system cannot meet the requirements of real-time circuit test and life prediction

Images