Nano-tubes semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. A nano-tubes area is produced by adopting the thin epitaxial layer formed on the channel sidewall of the semiconductor body. The thin epitaxial layer possesses an even and consistent dosage concentration. A first thin epitaxial layer in the same conducting type as the semiconductor body is formed on the channel sidewall of the semiconductor body. A second thin expitaxial layer in the opposite conducting type with the semiconductor body is formed on a first expitaxial layer. The first and the second expitaxial layer possess an even and consistent dosage concentration. An electric charge balance is achieved by choosing an appropriate first and second expitaxial layer and appropriate thickness and dosage concentration of the semiconductor body. The semiconductor body is a P-shaped substrate with light dosage. By adopting the N-expitaxial layer / P-expitaxial layer nano-tubes structure of the same type, a metal oxide field effect tube with a vertical channel, a insulated gate dipole transistor, a Schottky diode and a P-N diode can be produced.

Description

technical field [0001] The invention relates to a nanotube vertical channel metal oxide silicon field effect tube semiconductor device, in particular to a process for preparing a nanotube vertical channel metal oxide silicon field effect tube device through a side wall epitaxial layer. Furthermore, the present invention relates to edge termination structures in charge balancing power devices. Background technique [0002] Mosfet devices are formed through various lateral and vertical structures. Although lateral mosfet devices have fast switching speeds, they are not as dense as vertical mosfets. Vertical mosfet devices can be used to fabricate high-density arrays of transistors, but typical vertical mosfets have large gate-drain capacitance (Cgd) and drain-source capacitance (Cds). Therefore, the switching speed of the vertical MOSFET device is lower. Shielded gate structure transistors have low gate-drain capacitance (Cgd), but due to the non-self-aligning nature of the...

AI Technical Summary

Problems solved by technology

Shielded gate structure transistors have low gate-drain capacitance (Cgd), but due to the non-self-aligning nature of the gate oxide and N-drift region overlap, shielded gate structure transistor devices increase the drain-source "on" resistance (Rdson) range of variation

In addition, the unit step process of polysilicon electrode, interpolysilicon dielectric (IPD) and channel etching (side wall angle) makes the processing technology of shielded gate structure transistor complex and expensive

Also, the increase in output capacitance and shielded gate polysilicon resistance reduces the switching speed of shielded gate structure transistors

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