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Silicon transverse device on N-type insulator for improving current density and preparation process thereof

A silicon-on-insulator, lateral device technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of increasing current density, increasing device current, and saving manufacturing costs

Active Publication Date: 2013-01-02
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This has also become a difficult problem in the design of power devices

Method used

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  • Silicon transverse device on N-type insulator for improving current density and preparation process thereof
  • Silicon transverse device on N-type insulator for improving current density and preparation process thereof
  • Silicon transverse device on N-type insulator for improving current density and preparation process thereof

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Embodiment Construction

[0035] refer to figure 2 , an N-type silicon-on-insulator lateral device for increasing current density, comprising: a P-type semiconductor substrate 9 is provided with a buried oxide layer 8 on the semiconductor substrate 9, a P epitaxial layer 6 is provided on the buried oxide layer 8, and The P epitaxial layer is provided with an N-type drift region 7 and a P-type well region 15, and an N-type source region 12 and a P-type contact region 11 are arranged on the surface of the P-well region 15, and an N-type drift region 7 is provided on the N-type drift region 7. The buffer zone 14 is provided with a P-type drain region 10 above the N-type buffer zone 14, and a gate oxide layer 3 is also provided on the surface of the P epitaxial layer 6, and the gate oxide layer 3 extends from the P epitaxial layer 6 to the N-type drift Region 7, in the N-type source region 12 and the P-type contact region 11 on the surface of the type P well region 15, a field oxide layer 1 is provided on...

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Abstract

The invention relates to a silicon transverse device on an N-type insulator for improving current density, which comprises a semiconductor substrate, wherein a buried oxide layer is arranged on the semiconductor substrate; a P-type epitaxial layer is arranged on the buried oxide layer; an N-type drift region and a P-type well region are arranged on the P-type epitaxial layer; an N-type source region and a P-type contact region are arranged on the surface of the P-type well region; an N-type buffer region and a P-type drain region are arranged on the N-type drift region; a gate oxide is also arranged on the surface of the P-type epitaxial layer; the N-type source region and the P-type contact region are arranged on the surface of the P-type well region; and a field oxide is arranged on theregion on the surface of the N-type drift region outside the P-type drain region. The invention is characterized in that the N-type buffer region of the silicon transverse device on the N-type insulator is an annular buffer region, and the annular buffer region diffuses inward to form an N-type buffer diffusion region. The preparation process of the device comprises the following concrete steps: growing the P-type epitaxial layer on a silicon on insulator (SOI); preparing the N-type drift region and the P-type well region; preparing the annular N-type buffer region; preparing the field oxide and the gate oxide; preparing a polysilicon gate; preparing the source region and the drain region; punching holes; and preparing a metal layer.

Description

Technical field: [0001] The invention relates to the field of power semiconductor devices, and more specifically relates to an N-type silicon-on-insulator lateral device with increased current density and a preparation process thereof suitable for high-voltage and high-current applications. Background technique: [0002] With the increasing demand for modern life, the performance of power integrated circuits has attracted more and more attention. Among them, the ability of power integrated circuits to handle high voltage and high current has become one of the most important performance indicators. The factors that determine the ability of power integrated circuits to handle high voltage and high current are not only the circuit structure and design of the power integrated circuit itself, but also the manufacturing process adopted by the circuit. The current capability that a single device with the same area can pass is a measure of the performance and The key to cost. [00...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L29/06H01L21/265
Inventor 钱钦松刘斯扬孙伟锋陆生礼时龙兴
Owner SOUTHEAST UNIV
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