Method for constructing floating gate

Abstract

The invention discloses a method for constructing a floating gate, comprising the following steps: A. successively depositing a silicon oxide film and a silicon nitride film on the upper surface of the silicon substrate of a wafer; B. defining a shallow trench graph on the wafer in the processes of shallow trench photoetching and silicon nitride etching; C. after the silicon oxide is deposited inthe shallow trench, carrying out first planarization processing on the upper surface of the wafer; D. removing the silicon nitride, forming a vacancy on the original position of the silicon nitride, forming a protective gap wall on the side wall of the silicon oxide, wherein the reaction rate of the protective gap wall and hydrofluoric acid is less than the reaction rate of the silicon oxide and the hydrofluoric acid; E. pre-cleaning the surface of the wafer by acid solution which takes the hydrofluoric acid as a main ingredient, growing a gate oxide layer on the surface of the wafer, and depositing polycrystalline silicon on the vacancy; and F. carrying out secondary planarization processing to the upper surface of the wafer, and mutually separating polycrystalline silicon in different vacancies to form the floating gate.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for constructing a floating gate. Background technique [0002] Self-aligned-Process (SAP) is widely used in flash memory because it can achieve good self-alignment performance between floating gate (Floating Gate, FG) and shallow trench isolation (Shallow Trench Isolation, STI). (flash memory) storage unit manufacturing process. [0003] figure 1 A schematic diagram showing changes in a typical structural section of a wafer during the manufacturing process of a data storage unit (bit-cell) of a split-gate (Split-Gate) memory in the prior art. The initial wafer is a silicon substrate, a silicon oxide film is deposited on the upper surface, and a silicon nitride film is deposited on the silicon oxide film. Through the STI etching (STI-ET)-process, a shallow trench pattern is defined on the wafer, and the fragment section with typi...

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Problems solved by technology

Worse, too small spacing between FGs may cause a short circuit between adjacent FGs, resulting in device failure

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